From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Romanick Subject: Re: [PATCH] [WIP] i965: Use up to 80 WM threads on GT2. Date: Mon, 28 Mar 2011 15:22:35 -0700 Message-ID: <4D910A2B.3030606@freedesktop.org> References: <1301334940-18506-1-git-send-email-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from expn.cat.pdx.edu (expn.cat.pdx.edu [131.252.208.110]) by gabe.freedesktop.org (Postfix) with ESMTP id C081A9E755 for ; Mon, 28 Mar 2011 15:22:37 -0700 (PDT) In-Reply-To: <1301334940-18506-1-git-send-email-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eric Anholt Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 03/28/2011 10:55 AM, Eric Anholt wrote: > Here's an idea for an SNB performance improvement from the specs. It > says that on GT2 you should be able to use 80 threads if "WIZ Hashing > Disable in GT_MODE register enabled". On my system (supposedly GT2), > that bit (bit 6 of 0x20d0) is unset. In testing, with intel_reg_write > 0x20d0 0x00400040 (it only successfully took once, I suspect due to > FORCEWAKE, which also means that I can't necessarily trust that the > bit was unset originally), I got only hangs from 3D. So, we're currently using too many threads in some cases? Could this be related to bug #35730? In that case the failure seems to be limited to SugarBay. I believe that's GT1, but I can never get the code names for these chips straight. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org/ iEYEARECAAYFAk2RCisACgkQX1gOwKyEAw8nRgCgnC1HMyfVwx5MLiaVF4mVzprQ oD4An2DMFJdXfYKOyvehR7x6qAQnYix6 =4m/t -----END PGP SIGNATURE-----