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From: Shuang He <shuang.he@intel.com>
To: Ian Romanick <idr@freedesktop.org>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] [WIP] i965: Use up to 80 WM threads on GT2.
Date: Tue, 29 Mar 2011 08:32:04 +0800	[thread overview]
Message-ID: <4D912884.1050100@intel.com> (raw)
In-Reply-To: <4D910A2B.3030606@freedesktop.org>

On 2011/3/29 6:22, Ian Romanick wrote:
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> On 03/28/2011 10:55 AM, Eric Anholt wrote:
>
>> Here's an idea for an SNB performance improvement from the specs.  It
>> says that on GT2 you should be able to use 80 threads if "WIZ Hashing
>> Disable in GT_MODE register enabled".  On my system (supposedly GT2),
>> that bit (bit 6 of 0x20d0) is unset.  In testing, with intel_reg_write
>> 0x20d0 0x00400040 (it only successfully took once, I suspect due to
>> FORCEWAKE, which also means that I can't necessarily trust that the
>> bit was unset originally), I got only hangs from 3D.
> So, we're currently using too many threads in some cases?  Could this be
> related to bug #35730?  In that case the failure seems to be limited to
> SugarBay.  I believe that's GT1, but I can never get the code names for
> these chips straight.

The system environment description section in bug #35730 already mention 
it's rev09 GT1

Thanks
     --Shuang

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> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2011-03-29  0:32 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-03-28 17:55 [PATCH] [WIP] i965: Use up to 80 WM threads on GT2 Eric Anholt
2011-03-28 22:22 ` Ian Romanick
2011-03-29  0:32   ` Shuang He [this message]
2011-03-29  4:43   ` Eric Anholt
2011-03-29  6:52     ` Chris Wilson
2011-03-28 22:37 ` Ben Widawsky
2011-03-29  4:46   ` Eric Anholt

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