diff for duplicates of <4DC13252.2080308@ti.com> diff --git a/a/1.txt b/N1/1.txt index 440bed0..f17cbfc 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -232,3 +232,10 @@ unsigned int irq) #endif -- 1.6.0.4 + + + +-------------- next part -------------- +An embedded and charset-unspecified text was scrubbed... +Name: 0001-ARM-GIC-Convert-GIC-library-to-use-the-IO-relaxed.patch +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20110504/1a89444d/attachment.ksh> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index 20624bc..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,5 +0,0 @@ -Content-Type: text/plain; - name="0001-ARM-GIC-Convert-GIC-library-to-use-the-IO-relaxed.patch" -Content-Transfer-Encoding: base64 -Content-Disposition: attachment; - filename*0="0001-ARM-GIC-Convert-GIC-library-to-use-the-IO-relaxed.patch" diff --git a/a/2.txt b/a/2.txt deleted file mode 100644 index c33c4ed..0000000 --- a/a/2.txt +++ /dev/null @@ -1,198 +0,0 @@ -From 1506abc77b36eb10ae0e3f8711e6ad1b87ca363d Mon Sep 17 00:00:00 2001 -From: Santosh Shilimkar <santosh.shilimkar@ti.com> -Date: Mon, 28 Mar 2011 19:27:46 +0530 -Subject: [PATCH] ARM: GIC: Convert GIC library to use the IO relaxed operations - -The GIC register accesses today make use of readl()/writel() -which prove to be very expensive when used along with mandatory -barriers. This mandatory barriers also introduces an un-necessary -and expensive l2x0_sync() operation. On Cortex-A9 MP cores, GIC -IO accesses from CPU are direct and doesn't go through L2X0 write -buffer. - -A DSB before writel_relaxed() in gic_raise_softirq() is added to be -compliant with the Barrier Litmus document - the mailbox scenario. - -Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> -Acked-by: Catalin Marinas <catalin.marinas@arm.com> -Cc: Will Deacon <will.deacon@arm.com> ---- - arch/arm/common/gic.c | 54 +++++++++++++++++++++++++++--------------------- - 1 files changed, 30 insertions(+), 24 deletions(-) - -diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c -index e9c2ff8..4ddd0a6 100644 ---- a/arch/arm/common/gic.c -+++ b/arch/arm/common/gic.c -@@ -89,7 +89,7 @@ static void gic_mask_irq(struct irq_data *d) - u32 mask = 1 << (d->irq % 32); - - spin_lock(&irq_controller_lock); -- writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); -+ writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); - if (gic_arch_extn.irq_mask) - gic_arch_extn.irq_mask(d); - spin_unlock(&irq_controller_lock); -@@ -102,7 +102,7 @@ static void gic_unmask_irq(struct irq_data *d) - spin_lock(&irq_controller_lock); - if (gic_arch_extn.irq_unmask) - gic_arch_extn.irq_unmask(d); -- writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); -+ writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); - spin_unlock(&irq_controller_lock); - } - -@@ -114,7 +114,7 @@ static void gic_eoi_irq(struct irq_data *d) - spin_unlock(&irq_controller_lock); - } - -- writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); -+ writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); - } - - static int gic_set_type(struct irq_data *d, unsigned int type) -@@ -140,7 +140,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) - if (gic_arch_extn.irq_set_type) - gic_arch_extn.irq_set_type(d, type); - -- val = readl(base + GIC_DIST_CONFIG + confoff); -+ val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); - if (type == IRQ_TYPE_LEVEL_HIGH) - val &= ~confmask; - else if (type == IRQ_TYPE_EDGE_RISING) -@@ -150,15 +150,15 @@ static int gic_set_type(struct irq_data *d, unsigned int type) - * As recommended by the spec, disable the interrupt before changing - * the configuration - */ -- if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { -- writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); -+ if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { -+ writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); - enabled = true; - } - -- writel(val, base + GIC_DIST_CONFIG + confoff); -+ writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); - - if (enabled) -- writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); -+ writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); - - spin_unlock(&irq_controller_lock); - -@@ -190,8 +190,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, - - spin_lock(&irq_controller_lock); - d->node = cpu; -- val = readl(reg) & ~mask; -- writel(val | bit, reg); -+ val = readl_relaxed(reg) & ~mask; -+ writel_relaxed(val | bit, reg); - spin_unlock(&irq_controller_lock); - - return 0; -@@ -223,7 +223,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) - chained_irq_enter(chip, desc); - - spin_lock(&irq_controller_lock); -- status = readl(chip_data->cpu_base + GIC_CPU_INTACK); -+ status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK); - spin_unlock(&irq_controller_lock); - - gic_irq = (status & 0x3ff); -@@ -272,13 +272,13 @@ static void __init gic_dist_init(struct gic_chip_data *gic, - cpumask |= cpumask << 8; - cpumask |= cpumask << 16; - -- writel(0, base + GIC_DIST_CTRL); -+ writel_relaxed(0, base + GIC_DIST_CTRL); - - /* - * Find out how many interrupts are supported. - * The GIC only supports up to 1020 interrupt sources. - */ -- gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f; -+ gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f; - gic_irqs = (gic_irqs + 1) * 32; - if (gic_irqs > 1020) - gic_irqs = 1020; -@@ -287,26 +287,26 @@ static void __init gic_dist_init(struct gic_chip_data *gic, - * Set all global interrupts to be level triggered, active low. - */ - for (i = 32; i < gic_irqs; i += 16) -- writel(0, base + GIC_DIST_CONFIG + i * 4 / 16); -+ writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); - - /* - * Set all global interrupts to this CPU only. - */ - for (i = 32; i < gic_irqs; i += 4) -- writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); -+ writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); - - /* - * Set priority on all global interrupts. - */ - for (i = 32; i < gic_irqs; i += 4) -- writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); -+ writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); - - /* - * Disable all interrupts. Leave the PPI and SGIs alone - * as these enables are banked registers. - */ - for (i = 32; i < gic_irqs; i += 32) -- writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); -+ writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); - - /* - * Limit number of interrupts registered to the platform maximum -@@ -324,7 +324,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic, - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } - -- writel(1, base + GIC_DIST_CTRL); -+ writel_relaxed(1, base + GIC_DIST_CTRL); - } - - static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) -@@ -337,17 +337,17 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) - * Deal with the banked PPI and SGI interrupts - disable all - * PPI interrupts, ensure all SGI interrupts are enabled. - */ -- writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); -- writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); -+ writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); -+ writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); - - /* - * Set priority on PPI and SGI interrupts - */ - for (i = 0; i < 32; i += 4) -- writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); -+ writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); - -- writel(0xf0, base + GIC_CPU_PRIMASK); -- writel(1, base + GIC_CPU_CTRL); -+ writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); -+ writel_relaxed(1, base + GIC_CPU_CTRL); - } - - void __init gic_init(unsigned int gic_nr, unsigned int irq_start, -@@ -391,7 +391,13 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) - { - unsigned long map = *cpus_addr(*mask); - -+ /* -+ * Ensure that stores to Normal memory are visible to the -+ * other CPUs before issuing the IPI. -+ */ -+ dsb(); -+ - /* this always happens on GIC0 */ -- writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); -+ writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); - } - #endif --- -1.6.0.4 diff --git a/a/content_digest b/N1/content_digest index e3630c5..17437b7 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,14 +1,11 @@ "ref\01304058131-8375-1-git-send-email-santosh.shilimkar@ti.com\0" "ref\01304417481.19196.60.camel@e102109-lin.cambridge.arm.com\0" "ref\04DBFD59D.50008@ti.com\0" - "From\0Santosh Shilimkar <santosh.shilimkar@ti.com>\0" - "Subject\0Re: [PATCH V3] ARM: GIC: Convert GIC library to use the IO relaxed operations\0" + "From\0santosh.shilimkar@ti.com (Santosh Shilimkar)\0" + "Subject\0[PATCH V3] ARM: GIC: Convert GIC library to use the IO relaxed operations\0" "Date\0Wed, 04 May 2011 16:32:42 +0530\0" - "To\0Catalin Marinas <catalin.marinas@arm.com>" - " Will Deacon <Will.Deacon@arm.com>\0" - "Cc\0linux-arm-kernel@lists.infradead.org" - " linux-omap@vger.kernel.org\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "On 5/3/2011 3:44 PM, Santosh Shilimkar wrote:\n" "> On 5/3/2011 3:41 PM, Catalin Marinas wrote:\n" @@ -243,207 +240,13 @@ " }\n" " #endif\n" "-- \n" - 1.6.0.4 - "\01:2\0" - "fn\00001-ARM-GIC-Convert-GIC-library-to-use-the-IO-relaxed.patch\0" - "b\0" - "From 1506abc77b36eb10ae0e3f8711e6ad1b87ca363d Mon Sep 17 00:00:00 2001\n" - "From: Santosh Shilimkar <santosh.shilimkar@ti.com>\n" - "Date: Mon, 28 Mar 2011 19:27:46 +0530\n" - "Subject: [PATCH] ARM: GIC: Convert GIC library to use the IO relaxed operations\n" + "1.6.0.4\n" "\n" - "The GIC register accesses today make use of readl()/writel()\n" - "which prove to be very expensive when used along with mandatory\n" - "barriers. This mandatory barriers also introduces an un-necessary\n" - "and expensive l2x0_sync() operation. On Cortex-A9 MP cores, GIC\n" - "IO accesses from CPU are direct and doesn't go through L2X0 write\n" - "buffer.\n" "\n" - "A DSB before writel_relaxed() in gic_raise_softirq() is added to be\n" - "compliant with the Barrier Litmus document - the mailbox scenario.\n" "\n" - "Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>\n" - "Acked-by: Catalin Marinas <catalin.marinas@arm.com>\n" - "Cc: Will Deacon <will.deacon@arm.com>\n" - "---\n" - " arch/arm/common/gic.c | 54 +++++++++++++++++++++++++++---------------------\n" - " 1 files changed, 30 insertions(+), 24 deletions(-)\n" - "\n" - "diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c\n" - "index e9c2ff8..4ddd0a6 100644\n" - "--- a/arch/arm/common/gic.c\n" - "+++ b/arch/arm/common/gic.c\n" - "@@ -89,7 +89,7 @@ static void gic_mask_irq(struct irq_data *d)\n" - " \tu32 mask = 1 << (d->irq % 32);\n" - " \n" - " \tspin_lock(&irq_controller_lock);\n" - "-\twritel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);\n" - "+\twritel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);\n" - " \tif (gic_arch_extn.irq_mask)\n" - " \t\tgic_arch_extn.irq_mask(d);\n" - " \tspin_unlock(&irq_controller_lock);\n" - "@@ -102,7 +102,7 @@ static void gic_unmask_irq(struct irq_data *d)\n" - " \tspin_lock(&irq_controller_lock);\n" - " \tif (gic_arch_extn.irq_unmask)\n" - " \t\tgic_arch_extn.irq_unmask(d);\n" - "-\twritel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);\n" - "+\twritel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);\n" - " \tspin_unlock(&irq_controller_lock);\n" - " }\n" - " \n" - "@@ -114,7 +114,7 @@ static void gic_eoi_irq(struct irq_data *d)\n" - " \t\tspin_unlock(&irq_controller_lock);\n" - " \t}\n" - " \n" - "-\twritel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);\n" - "+\twritel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);\n" - " }\n" - " \n" - " static int gic_set_type(struct irq_data *d, unsigned int type)\n" - "@@ -140,7 +140,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)\n" - " \tif (gic_arch_extn.irq_set_type)\n" - " \t\tgic_arch_extn.irq_set_type(d, type);\n" - " \n" - "-\tval = readl(base + GIC_DIST_CONFIG + confoff);\n" - "+\tval = readl_relaxed(base + GIC_DIST_CONFIG + confoff);\n" - " \tif (type == IRQ_TYPE_LEVEL_HIGH)\n" - " \t\tval &= ~confmask;\n" - " \telse if (type == IRQ_TYPE_EDGE_RISING)\n" - "@@ -150,15 +150,15 @@ static int gic_set_type(struct irq_data *d, unsigned int type)\n" - " \t * As recommended by the spec, disable the interrupt before changing\n" - " \t * the configuration\n" - " \t */\n" - "-\tif (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {\n" - "-\t\twritel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);\n" - "+\tif (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {\n" - "+\t\twritel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);\n" - " \t\tenabled = true;\n" - " \t}\n" - " \n" - "-\twritel(val, base + GIC_DIST_CONFIG + confoff);\n" - "+\twritel_relaxed(val, base + GIC_DIST_CONFIG + confoff);\n" - " \n" - " \tif (enabled)\n" - "-\t\twritel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);\n" - "+\t\twritel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);\n" - " \n" - " \tspin_unlock(&irq_controller_lock);\n" - " \n" - "@@ -190,8 +190,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,\n" - " \n" - " \tspin_lock(&irq_controller_lock);\n" - " \td->node = cpu;\n" - "-\tval = readl(reg) & ~mask;\n" - "-\twritel(val | bit, reg);\n" - "+\tval = readl_relaxed(reg) & ~mask;\n" - "+\twritel_relaxed(val | bit, reg);\n" - " \tspin_unlock(&irq_controller_lock);\n" - " \n" - " \treturn 0;\n" - "@@ -223,7 +223,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)\n" - " \tchained_irq_enter(chip, desc);\n" - " \n" - " \tspin_lock(&irq_controller_lock);\n" - "-\tstatus = readl(chip_data->cpu_base + GIC_CPU_INTACK);\n" - "+\tstatus = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);\n" - " \tspin_unlock(&irq_controller_lock);\n" - " \n" - " \tgic_irq = (status & 0x3ff);\n" - "@@ -272,13 +272,13 @@ static void __init gic_dist_init(struct gic_chip_data *gic,\n" - " \tcpumask |= cpumask << 8;\n" - " \tcpumask |= cpumask << 16;\n" - " \n" - "-\twritel(0, base + GIC_DIST_CTRL);\n" - "+\twritel_relaxed(0, base + GIC_DIST_CTRL);\n" - " \n" - " \t/*\n" - " \t * Find out how many interrupts are supported.\n" - " \t * The GIC only supports up to 1020 interrupt sources.\n" - " \t */\n" - "-\tgic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;\n" - "+\tgic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;\n" - " \tgic_irqs = (gic_irqs + 1) * 32;\n" - " \tif (gic_irqs > 1020)\n" - " \t\tgic_irqs = 1020;\n" - "@@ -287,26 +287,26 @@ static void __init gic_dist_init(struct gic_chip_data *gic,\n" - " \t * Set all global interrupts to be level triggered, active low.\n" - " \t */\n" - " \tfor (i = 32; i < gic_irqs; i += 16)\n" - "-\t\twritel(0, base + GIC_DIST_CONFIG + i * 4 / 16);\n" - "+\t\twritel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);\n" - " \n" - " \t/*\n" - " \t * Set all global interrupts to this CPU only.\n" - " \t */\n" - " \tfor (i = 32; i < gic_irqs; i += 4)\n" - "-\t\twritel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);\n" - "+\t\twritel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);\n" - " \n" - " \t/*\n" - " \t * Set priority on all global interrupts.\n" - " \t */\n" - " \tfor (i = 32; i < gic_irqs; i += 4)\n" - "-\t\twritel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);\n" - "+\t\twritel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);\n" - " \n" - " \t/*\n" - " \t * Disable all interrupts. Leave the PPI and SGIs alone\n" - " \t * as these enables are banked registers.\n" - " \t */\n" - " \tfor (i = 32; i < gic_irqs; i += 32)\n" - "-\t\twritel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);\n" - "+\t\twritel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);\n" - " \n" - " \t/*\n" - " \t * Limit number of interrupts registered to the platform maximum\n" - "@@ -324,7 +324,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic,\n" - " \t\tset_irq_flags(i, IRQF_VALID | IRQF_PROBE);\n" - " \t}\n" - " \n" - "-\twritel(1, base + GIC_DIST_CTRL);\n" - "+\twritel_relaxed(1, base + GIC_DIST_CTRL);\n" - " }\n" - " \n" - " static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)\n" - "@@ -337,17 +337,17 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)\n" - " \t * Deal with the banked PPI and SGI interrupts - disable all\n" - " \t * PPI interrupts, ensure all SGI interrupts are enabled.\n" - " \t */\n" - "-\twritel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);\n" - "-\twritel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);\n" - "+\twritel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);\n" - "+\twritel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);\n" - " \n" - " \t/*\n" - " \t * Set priority on PPI and SGI interrupts\n" - " \t */\n" - " \tfor (i = 0; i < 32; i += 4)\n" - "-\t\twritel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);\n" - "+\t\twritel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);\n" - " \n" - "-\twritel(0xf0, base + GIC_CPU_PRIMASK);\n" - "-\twritel(1, base + GIC_CPU_CTRL);\n" - "+\twritel_relaxed(0xf0, base + GIC_CPU_PRIMASK);\n" - "+\twritel_relaxed(1, base + GIC_CPU_CTRL);\n" - " }\n" - " \n" - " void __init gic_init(unsigned int gic_nr, unsigned int irq_start,\n" - "@@ -391,7 +391,13 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)\n" - " {\n" - " \tunsigned long map = *cpus_addr(*mask);\n" - " \n" - "+\t/*\n" - "+\t * Ensure that stores to Normal memory are visible to the\n" - "+\t * other CPUs before issuing the IPI.\n" - "+\t */\n" - "+\tdsb();\n" - "+\n" - " \t/* this always happens on GIC0 */\n" - "-\twritel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);\n" - "+\twritel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);\n" - " }\n" - " #endif\n" - "-- \n" - 1.6.0.4 + "-------------- next part --------------\n" + "An embedded and charset-unspecified text was scrubbed...\n" + "Name: 0001-ARM-GIC-Convert-GIC-library-to-use-the-IO-relaxed.patch\n" + URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20110504/1a89444d/attachment.ksh> -31a0d4766c9aad5faaaad4362c6698d9158f4935044000f00fd9ce36d9a4a52b +8abb9e32249cb2d89ecad49217478d86bd00229073a117bf4e5e196655470f67
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