From: Shinya Kuribayashi <skuribay@pobox.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [GIT PULL] MIPS patches
Date: Tue, 10 May 2011 00:17:09 +0900 [thread overview]
Message-ID: <4DC80575.8020401@pobox.com> (raw)
Hi,
Please pull the MIPS updates, thanks in advance.
--- 8< ---
The following changes since commit 96d04c3150ae9284500aef48803d7d132968f2b2:
IDE: fix compiler warnings (2011-04-30 23:29:55 +0200)
are available in the git repository at:
ssh://gu-mips@git.denx.de/u-boot-mips.git master
Daniel Schwierzeck (1):
MIPS: Introduce --gc-sections for MIPS
Shinya Kuribayashi (3):
MIPS: Remove mips_cache_lock() feature
MIPS: Coding style cleanups on common assembly files
MIPS: Move timer code to arch/mips/cpu/$(CPU)/
arch/mips/config.mk | 2 +
arch/mips/cpu/mips32/Makefile | 2 +-
arch/mips/cpu/mips32/cache.S | 174 ++++++++--------------------------
arch/mips/cpu/mips32/start.S | 124 +++++++++++--------------
arch/mips/{lib => cpu/mips32}/time.c | 0
arch/mips/lib/Makefile | 1 -
board/dbau1x00/u-boot.lds | 10 +-
board/gth2/u-boot.lds | 10 +-
board/incaip/u-boot.lds | 10 +-
board/micronas/vct/u-boot.lds | 10 +-
board/pb1x00/u-boot.lds | 10 +-
board/qemu-mips/u-boot.lds | 10 +-
board/tb0229/u-boot.lds | 10 +-
examples/standalone/mips.lds | 10 +-
14 files changed, 135 insertions(+), 248 deletions(-)
rename arch/mips/{lib => cpu/mips32}/time.c (100%)
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 318d34b..6ab8acd 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -50,3 +50,5 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic
PLATFORM_CPPFLAGS += -msoft-float
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+LDFLAGS_FINAL += --gc-sections
diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile
index e315c1b..eb8e005 100644
--- a/arch/mips/cpu/mips32/Makefile
+++ b/arch/mips/cpu/mips32/Makefile
@@ -27,7 +27,7 @@ LIB = $(obj)lib$(CPU).o
START = start.o
SOBJS-y = cache.o
-COBJS-y = cpu.o interrupts.o
+COBJS-y = cpu.o interrupts.o time.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 2965938..5ce0ec4 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -51,75 +51,6 @@
.set pop
.endm
-/*
- * cacheop macro to automate cache operations
- * first some helpers...
- */
-#define _mincache(size, maxsize) \
- bltu size,maxsize,9f ; \
- move size,maxsize ; \
-9:
-
-#define _align(minaddr, maxaddr, linesize) \
- .set noat ; \
- subu AT,linesize,1 ; \
- not AT ; \
- and minaddr,AT ; \
- addu maxaddr,-1 ; \
- and maxaddr,AT ; \
- .set at
-
-/* general operations */
-#define doop1(op1) \
- cache op1,0(a0)
-#define doop2(op1, op2) \
- cache op1,0(a0) ; \
- nop ; \
- cache op2,0(a0)
-
-/* specials for cache initialisation */
-#define doop1lw(op1) \
- lw zero,0(a0)
-#define doop1lw1(op1) \
- cache op1,0(a0) ; \
- lw zero,0(a0) ; \
- cache op1,0(a0)
-#define doop121(op1,op2) \
- cache op1,0(a0) ; \
- nop; \
- cache op2,0(a0) ; \
- nop; \
- cache op1,0(a0)
-
-#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
- .set noreorder ; \
-10: doop##tag##ops ; \
- bne minaddr,maxaddr,10b ; \
- add minaddr,linesize ; \
- .set reorder
-
-/* finally the cache operation macros */
-#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
- blez n,11f ; \
- addu n,kva ; \
- _align(kva, n, cacheLineSize) ; \
- _oploopn(kva, n, cacheLineSize, tag, ops) ; \
-11:
-
-#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
- _mincache(n, cacheSize); \
- blez n,11f ; \
- addu n,kva ; \
- _align(kva, n, cacheLineSize) ; \
- _oploopn(kva, n, cacheLineSize, tag, ops) ; \
-11:
-
-#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
- vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
-
-#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
- icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
-
.macro f_fill64 dst, offset, val
LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
@@ -145,8 +76,8 @@
* mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
*/
LEAF(mips_init_icache)
- blez a1, 9f
- mtc0 zero, CP0_TAGLO
+ blez a1, 9f
+ mtc0 zero, CP0_TAGLO
/* clear tag to invalidate */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
@@ -163,15 +94,15 @@ LEAF(mips_init_icache)
1: cache_op Index_Store_Tag_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
-9: jr ra
+9: jr ra
END(mips_init_icache)
/*
* mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
*/
LEAF(mips_init_dcache)
- blez a1, 9f
- mtc0 zero, CP0_TAGLO
+ blez a1, 9f
+ mtc0 zero, CP0_TAGLO
/* clear all tags */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
@@ -188,25 +119,23 @@ LEAF(mips_init_dcache)
1: cache_op Index_Store_Tag_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
-9: jr ra
+9: jr ra
END(mips_init_dcache)
-/*******************************************************************************
-*
-* mips_cache_reset - low level initialisation of the primary caches
-*
-* This routine initialises the primary caches to ensure that they
-* have good parity. It must be called by the ROM before any cached locations
-* are used to prevent the possibility of data with bad parity being written to
-* memory.
-* To initialise the instruction cache it is essential that a source of data
-* with good parity is available. This routine
-* will initialise an area of memory starting at location zero to be used as
-* a source of parity.
-*
-* RETURNS: N/A
-*
-*/
+/*
+ * mips_cache_reset - low level initialisation of the primary caches
+ *
+ * This routine initialises the primary caches to ensure that they have good
+ * parity. It must be called by the ROM before any cached locations are used
+ * to prevent the possibility of data with bad parity being written to memory.
+ *
+ * To initialise the instruction cache it is essential that a source of data
+ * with good parity is available. This routine will initialise an area of
+ * memory starting at location zero to be used as a source of parity.
+ *
+ * RETURNS: N/A
+ *
+ */
NESTED(mips_cache_reset, 0, ra)
move RA, ra
li t2, CONFIG_SYS_ICACHE_SIZE
@@ -254,13 +183,12 @@ NESTED(mips_cache_reset, 0, ra)
jr RA
END(mips_cache_reset)
-/*******************************************************************************
-*
-* dcache_status - get cache status
-*
-* RETURNS: 0 - cache disabled; 1 - cache enabled
-*
-*/
+/*
+ * dcache_status - get cache status
+ *
+ * RETURNS: 0 - cache disabled; 1 - cache enabled
+ *
+ */
LEAF(dcache_status)
mfc0 t0, CP0_CONFIG
li t1, CONF_CM_UNCACHED
@@ -271,13 +199,12 @@ LEAF(dcache_status)
2: jr ra
END(dcache_status)
-/*******************************************************************************
-*
-* dcache_disable - disable cache
-*
-* RETURNS: N/A
-*
-*/
+/*
+ * dcache_disable - disable cache
+ *
+ * RETURNS: N/A
+ *
+ */
LEAF(dcache_disable)
mfc0 t0, CP0_CONFIG
li t1, -8
@@ -287,13 +214,12 @@ LEAF(dcache_disable)
jr ra
END(dcache_disable)
-/*******************************************************************************
-*
-* dcache_enable - enable cache
-*
-* RETURNS: N/A
-*
-*/
+/*
+ * dcache_enable - enable cache
+ *
+ * RETURNS: N/A
+ *
+ */
LEAF(dcache_enable)
mfc0 t0, CP0_CONFIG
ori t0, CONF_CM_CMASK
@@ -302,27 +228,3 @@ LEAF(dcache_enable)
mtc0 t0, CP0_CONFIG
jr ra
END(dcache_enable)
-
-#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
-/*******************************************************************************
-*
-* mips_cache_lock - lock RAM area pointed to by a0 in cache.
-*
-* RETURNS: N/A
-*
-*/
-# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
- .globl mips_cache_lock
- .ent mips_cache_lock
-mips_cache_lock:
- li a1, CKSEG0 - CACHE_LOCK_SIZE
- addu a0, a1
- li a2, CACHE_LOCK_SIZE
- li a3, CONFIG_SYS_CACHELINE_SIZE
- move a1, a2
- icacheop(a0,a1,a2,a3,0x1d)
-
- jr ra
-
- .end mips_cache_lock
-#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index e661d46..5d7467d 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -62,11 +62,11 @@
.globl _start
.text
_start:
- RVECENT(reset,0) /* U-boot entry point */
- RVECENT(reset,1) /* software reboot */
-#if defined(CONFIG_INCA_IP)
- .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
- .word 0x00000000 /* phase of the flash */
+ RVECENT(reset,0) # U-boot entry point
+ RVECENT(reset,1) # software reboot
+#ifdef CONFIG_INCA_IP
+ .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during
+ .word 0x00000000 # booting phase of the flash
#else
RVECENT(romReserved,2)
#endif
@@ -131,7 +131,7 @@ _start:
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
- XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
+ XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
@@ -147,7 +147,7 @@ _start:
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
- XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
+ XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
@@ -163,7 +163,7 @@ _start:
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
- XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
+ XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
@@ -179,7 +179,7 @@ _start:
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
- XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
+ XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
@@ -196,19 +196,19 @@ _start:
RVECENT(romReserved,126)
RVECENT(romReserved,127)
- /* We hope there are no more reserved vectors!
+ /*
+ * We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
.align 4
reset:
- /* Clear watch registers.
- */
+ /* Clear watch registers */
mtc0 zero, CP0_WATCHLO
mtc0 zero, CP0_WATCHHI
- /* WP(Watch Pending), SW0/1 should be cleared. */
+ /* WP(Watch Pending), SW0/1 should be cleared */
mtc0 zero, CP0_CAUSE
setup_c0_status_reset
@@ -217,54 +217,42 @@ reset:
mtc0 zero, CP0_COUNT
mtc0 zero, CP0_COMPARE
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/* CONFIG0 register */
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
+#endif
- /* Initialize $gp.
- */
+ /* Initialize $gp */
bal 1f
- nop
+ nop
.word _gp
1:
lw gp, 0(ra)
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
- /* Initialize any external memory.
- */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* Initialize any external memory */
la t9, lowlevel_init
jalr t9
- nop
+ nop
- /* Initialize caches...
- */
+ /* Initialize caches... */
la t9, mips_cache_reset
jalr t9
- nop
+ nop
- /* ... and enable them.
- */
+ /* ... and enable them */
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
-
- /* Set up temporary stack.
- */
-#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
- li a0, CONFIG_SYS_INIT_SP_OFFSET
- la t9, mips_cache_lock
- jalr t9
- nop
#endif
+ /* Set up temporary stack */
li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
la sp, 0(t0)
la t9, board_init_f
jr t9
- nop
+ nop
/*
* void relocate_code (addr_sp, gd, addr_moni)
@@ -279,13 +267,13 @@ reset:
.globl relocate_code
.ent relocate_code
relocate_code:
- move sp, a0 /* Set new stack pointer */
+ move sp, a0 # set new stack pointer
li t0, CONFIG_SYS_MONITOR_BASE
la t3, in_ram
- lw t2, -12(t3) /* t2 <-- uboot_end_data */
+ lw t2, -12(t3) # t2 <-- uboot_end_data
move t1, a2
- move s2, a2 /* s2 <-- destination address */
+ move s2, a2 # s2 <-- destination address
/*
* Fix $gp:
@@ -294,8 +282,8 @@ relocate_code:
*/
move t6, gp
sub gp, CONFIG_SYS_MONITOR_BASE
- add gp, a2 /* gp now adjusted */
- sub s1, gp, t6 /* s1 <-- relocation offset */
+ add gp, a2 # gp now adjusted
+ sub s1, gp, t6 # s1 <-- relocation offset
/*
* t0 = source address
@@ -306,30 +294,28 @@ relocate_code:
/*
* Save destination address and size for later usage in flush_cache()
*/
- move s0, a1 /* save gd in s0 */
- move a0, t1 /* a0 <-- destination addr */
- sub a1, t2, t0 /* a1 <-- size */
+ move s0, a1 # save gd in s0
+ move a0, t1 # a0 <-- destination addr
+ sub a1, t2, t0 # a1 <-- size
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
- addu t1, 4 /* delay slot */
+ addu t1, 4
- /* If caches were enabled, we would have to flush them here.
- */
+ /* If caches were enabled, we would have to flush them here. */
/* a0 & a1 are already set up for flush_cache(start, size) */
la t9, flush_cache
jalr t9
- nop
+ nop
- /* Jump to where we've relocated ourselves.
- */
+ /* Jump to where we've relocated ourselves */
addi t0, s2, in_ram - _start
jr t0
- nop
+ nop
.word _gp
.word _GLOBAL_OFFSET_TABLE_
@@ -344,45 +330,43 @@ in_ram:
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
* generated by GNU ld. Skip these reserved entries from relocation.
*/
- lw t3, -4(t0) /* t3 <-- num_got_entries */
- lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */
- lw t5, -20(t0) /* t5 <-- _gp */
- sub t4, t5 /* compute offset*/
- add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */
- addi t4, t4, 8 /* Skipping first two entries. */
+ lw t3, -4(t0) # t3 <-- num_got_entries
+ lw t4, -16(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
+ lw t5, -20(t0) # t5 <-- _gp
+ sub t4, t5 # compute offset
+ add t4, t4, gp # t4 now holds relocated _G_O_T_
+ addi t4, t4, 8 # skipping first two entries
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
- add t1, s1
+ add t1, s1
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
- addi t4, 4 /* delay slot */
+ addi t4, 4
- /* Clear BSS.
- */
- lw t1, -12(t0) /* t1 <-- uboot_end_data */
- lw t2, -8(t0) /* t2 <-- uboot_end */
- add t1, s1 /* adjust pointers */
+ /* Clear BSS */
+ lw t1, -12(t0) # t1 <-- uboot_end_data
+ lw t2, -8(t0) # t2 <-- uboot_end
+ add t1, s1 # adjust pointers
add t2, s1
sub t1, 4
1:
addi t1, 4
bltl t1, t2, 1b
- sw zero, 0(t1) /* delay slot */
+ sw zero, 0(t1)
- move a0, s0 /* a0 <-- gd */
+ move a0, s0 # a0 <-- gd
la t9, board_init_r
jr t9
- move a1, s2 /* delay slot */
+ move a1, s2
.end relocate_code
- /* Exception handlers.
- */
+ /* Exception handlers */
romReserved:
b romReserved
diff --git a/arch/mips/lib/time.c b/arch/mips/cpu/mips32/time.c
similarity index 100%
rename from arch/mips/lib/time.c
rename to arch/mips/cpu/mips32/time.c
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 4e90704..9244f31 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -33,7 +33,6 @@ COBJS-y += bootm_qemu_mips.o
else
COBJS-y += bootm.o
endif
-COBJS-y += time.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds
index 3c4fbe3..4a59cea 100644
--- a/board/dbau1x00/u-boot.lds
+++ b/board/dbau1x00/u-boot.lds
@@ -34,14 +34,14 @@ SECTIONS
. = ALIGN(4);
.text :
{
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
@@ -52,7 +52,7 @@ SECTIONS
__got_end = .;
}
- .sdata : { *(.sdata) }
+ .sdata : { *(.sdata*) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
@@ -64,7 +64,7 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss) }
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
uboot_end = .;
}
diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds
index aeb0fcc..9fc417f 100644
--- a/board/gth2/u-boot.lds
+++ b/board/gth2/u-boot.lds
@@ -34,14 +34,14 @@ SECTIONS
. = ALIGN(4);
.text :
{
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
@@ -52,7 +52,7 @@ SECTIONS
__got_end = .;
}
- .sdata : { *(.sdata) }
+ .sdata : { *(.sdata*) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
@@ -64,7 +64,7 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss) }
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
uboot_end = .;
}
diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds
index 3c4fbe3..4a59cea 100644
--- a/board/incaip/u-boot.lds
+++ b/board/incaip/u-boot.lds
@@ -34,14 +34,14 @@ SECTIONS
. = ALIGN(4);
.text :
{
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
@@ -52,7 +52,7 @@ SECTIONS
__got_end = .;
}
- .sdata : { *(.sdata) }
+ .sdata : { *(.sdata*) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
@@ -64,7 +64,7 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss) }
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
uboot_end = .;
}
diff --git a/board/micronas/vct/u-boot.lds b/board/micronas/vct/u-boot.lds
index b90b186..3a05ef9 100644
--- a/board/micronas/vct/u-boot.lds
+++ b/board/micronas/vct/u-boot.lds
@@ -31,14 +31,14 @@ SECTIONS
. = ALIGN(4);
.text :
{
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
@@ -50,7 +50,7 @@ SECTIONS
}
. = ALIGN(4);
- .sdata : { *(.sdata) }
+ .sdata : { *(.sdata*) }
. = ALIGN(4);
.u_boot_cmd : {
@@ -64,8 +64,8 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss) }
+ .sbss (NOLOAD) : { *(.sbss*) }
. = ALIGN(4);
- .bss (NOLOAD) : { *(.bss) }
+ .bss (NOLOAD) : { *(.bss*) }
uboot_end = .;
}
diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds
index 358cc54..bd0dee1 100644
--- a/board/pb1x00/u-boot.lds
+++ b/board/pb1x00/u-boot.lds
@@ -34,14 +34,14 @@ SECTIONS
. = ALIGN(4);
.text :
{
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
@@ -52,7 +52,7 @@ SECTIONS
__got_end = .;
}
- .sdata : { *(.sdata) }
+ .sdata : { *(.sdata*) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
@@ -64,7 +64,7 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss) }
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
uboot_end = .;
}
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index bd16786..9460b20 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -34,14 +34,14 @@ SECTIONS
. = ALIGN(4);
.text :
{
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = .;
_gp = ALIGN(16) +0x7ff0;
@@ -53,7 +53,7 @@ SECTIONS
}
. = ALIGN(4);
- .sdata : { *(.sdata) }
+ .sdata : { *(.sdata*) }
. = .;
.u_boot_cmd : {
@@ -66,7 +66,7 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
- .sbss : { *(.sbss) }
- .bss : { *(.bss) . = ALIGN(4); }
+ .sbss : { *(.sbss*) }
+ .bss : { *(.bss*) . = ALIGN(4); }
uboot_end = .;
}
diff --git a/board/tb0229/u-boot.lds b/board/tb0229/u-boot.lds
index 56d7c25..5ea1094 100644
--- a/board/tb0229/u-boot.lds
+++ b/board/tb0229/u-boot.lds
@@ -34,14 +34,14 @@ SECTIONS
. = ALIGN(4);
.text :
{
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
@@ -52,7 +52,7 @@ SECTIONS
__got_end = .;
}
- .sdata : { *(.sdata) }
+ .sdata : { *(.sdata*) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
@@ -64,7 +64,7 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss) }
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
uboot_end = .;
}
diff --git a/examples/standalone/mips.lds b/examples/standalone/mips.lds
index 63a1c92..5f766ed 100644
--- a/examples/standalone/mips.lds
+++ b/examples/standalone/mips.lds
@@ -30,14 +30,14 @@ SECTIONS
{
.text :
{
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
@@ -48,12 +48,12 @@ SECTIONS
__got_end = .;
}
- .sdata : { *(.sdata) }
+ .sdata : { *(.sdata*) }
. = ALIGN(4);
__bss_start = .;
- .sbss (NOLOAD) : { *(.sbss) }
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
_end = .;
}
next reply other threads:[~2011-05-09 15:17 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-09 15:17 Shinya Kuribayashi [this message]
2011-05-10 20:35 ` [U-Boot] [GIT PULL] MIPS patches Wolfgang Denk
-- strict thread matches above, loose matches on Subject: below --
2011-07-31 15:05 Shinya Kuribayashi
2011-08-02 19:46 ` Wolfgang Denk
2011-04-02 13:20 Shinya Kuribayashi
2011-04-05 10:17 ` Wolfgang Denk
2011-02-12 5:10 Shinya Kuribayashi
2011-02-12 19:38 ` Wolfgang Denk
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4DC80575.8020401@pobox.com \
--to=skuribay@pobox.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.