From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jacob Shin Subject: Re: [PATCH 2/3] xenoprof: Add support for AMD Family 15h processors Date: Tue, 10 May 2011 11:56:43 -0500 Message-ID: <4DC96E4B.9030906@amd.com> References: <4DC270D1020000780003FC66@vpn.id2.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <4DC270D1020000780003FC66@vpn.id2.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Jan Beulich Cc: "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org On 05/05/2011 02:41 AM, Jan Beulich wrote: >>>> On 05.05.11 at 03:09, Jacob Shin wrote: >> --- a/xen/include/asm-x86/msr-index.h Tue May 03 17:26:33 2011 -0500 >> +++ b/xen/include/asm-x86/msr-index.h Wed May 04 10:56:36 2011 -0500 >> @@ -223,6 +223,19 @@ >> #define MSR_K8_ENABLE_C1E 0xc0010055 >> #define MSR_K8_VM_CR 0xc0010114 >> #define MSR_K8_VM_HSAVE_PA 0xc0010117 >> + >> +#define MSR_FAM15H_EVNTSEL0 0xc0010200 >> +#define MSR_FAM15H_PERFCTR0 0xc0010201 >> +#define MSR_FAM15H_EVNTSEL1 0xc0010202 >> +#define MSR_FAM15H_PERFCTR1 0xc0010203 >> +#define MSR_FAM15H_EVNTSEL2 0xc0010204 >> +#define MSR_FAM15H_PERFCTR2 0xc0010205 >> +#define MSR_FAM15H_EVNTSEL3 0xc0010206 >> +#define MSR_FAM15H_PERFCTR3 0xc0010207 >> +#define MSR_FAM15H_EVNTSEL4 0xc0010208 >> +#define MSR_FAM15H_PERFCTR4 0xc0010209 >> +#define MSR_FAM15H_EVNTSEL5 0xc001020a >> +#define MSR_FAM15H_PERFCTR5 0xc001020b > > Oh, and all of these would better have AMD in their name, too > (other than K8, which really can be considered a product name, > Fam15 is too generic imo, as any vendor could have such at > some point). > Sounds good, I'll have a revised patchset with the changes later this afternoon. Thanks!