From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:33885) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QN3h1-0008Bd-7D for qemu-devel@nongnu.org; Thu, 19 May 2011 09:55:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QN3h0-0002B7-8H for qemu-devel@nongnu.org; Thu, 19 May 2011 09:55:11 -0400 Received: from david.siemens.de ([192.35.17.14]:26815) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QN3gz-0002Ay-VM for qemu-devel@nongnu.org; Thu, 19 May 2011 09:55:10 -0400 Message-ID: <4DD52138.9020204@siemens.com> Date: Thu, 19 May 2011 15:55:04 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <4DD3C5B9.1080908@redhat.com> <4DD3D236.90708@siemens.com> <4DD3D95E.2060105@redhat.com> <4DD3E1B3.3020405@siemens.com> <4DD3E47F.9060104@redhat.com> <4DD3E782.8090208@siemens.com> <4DD3E8D6.6090807@redhat.com> <20110519090851.GD28399@redhat.com> <4DD4DE8E.8030402@redhat.com> <4DD51EAC.4080505@codemonkey.ws> <4DD51F67.2070103@siemens.com> <4DD5202B.8070202@codemonkey.ws> In-Reply-To: <4DD5202B.8070202@codemonkey.ws> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC] Memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Avi Kivity , Gleb Natapov , qemu-devel On 2011-05-19 15:50, Anthony Liguori wrote: > On 05/19/2011 08:47 AM, Jan Kiszka wrote: >> On 2011-05-19 15:44, Anthony Liguori wrote: >>> Well...... >>> >>> The i440fx may direct VGA accesses to RAM depending on the SMM >>> registers. By the time the PIIX gets the I/O request, we're past the >>> memory controller. >>> >>> This is my biggest concern about this whole notion of "priority". These >>> sort of issues are not dealt with by a simple z-ordering. There is >>> logic in each component that may be arbitrarily complex. >>> >>> We're going to end up having to dynamically change the "priority" based >>> how registers are programmed. But priorities are relative so it's >>> unclear to me how the I440FX would prioritize RAM over dispatch to PIIX >>> (for VGA, for instance). >> >> But creating an extra RAM window region with higher priority than the >> underlying mappings. > > But the i440fx doesn't register the VGA region. The PIIX3 (ISA bus) > does, so how does it know what the priority of that mapping is? Everything imported from "below" is of default priority for a bridge. So it just has to add 1 to that prio value (or more if it needs to support more layers). Jan -- Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux