Re: [Qemu-devel] [PATCH 1/3] Add ppc_init_cacheline_sizes() function for OpenBSD.

[Brad <brad@comstyle.com>]

On 26/05/11 9:15 AM, malc wrote:
> On Thu, 26 May 2011, Brad wrote:
>
>> ----- Original message -----
>>> On Wed, 25 May 2011, Brad wrote:
>>>
>>>> Add ppc_init_cacheline_sizes() function for OpenBSD to fix compilation
>>>> of PowerPC host support for OpenBSD/powerpc based architectures.
>>>>
>>>> Signed-off-by: Brad Smith<brad@comstyle.com>
>>>>
>>>> ---
>>>> cache-utils.c |     11 +++++++++--
>>>> 1 files changed, 9 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/cache-utils.c b/cache-utils.c
>>>> index 2db5af2..c319705 100644
>>>> --- a/cache-utils.c
>>>> +++ b/cache-utils.c
>>>> @@ -55,9 +55,16 @@ static void ppc_init_cacheline_sizes(void)
>>>> qemu_cache_conf.icache_bsize = cacheline;
>>>> }
>>>> }
>>>> -#endif
>>>>
>>>> -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
>>>> +#elif defined(__OpenBSD__)
>>>> +
>>>> +static void ppc_init_cacheline_sizes(void)
>>>> +{
>>>> +       qemu_cache_conf.dcache_bsize = 32;
>>>> +       qemu_cache_conf.icache_bsize = 32;
>>>> +}
>>>> +
>>>> +#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
>>>> #include<errno.h>
>>>> #include<stdio.h>
>>>> #include<stdlib.h>
>>>>
>>>
>>> This can't be right for most ppc64's.
>>
>> Well this is what OpenBSD currently does and runs on G5's in 32-bit mode only.
>>
>
> Mode of operation does not, to the best of my knowledge, change the
> hardware limits, the cache line size will still be 128 on those G5s.

Well this is the behavior of our kernel no matter what the CPU type is.

from sys/arch/powerpc/cpu.h..


#define CACHELINE       32              /* Note that this value is 
really hardwired */


static __inline void
syncicache(void *from, int len)
{
	int l;
	char *p = from;

	len = len + (((u_int32_t) from) & (CACHELINESIZE - 1));
	l = len;

	do {
		__asm __volatile ("dcbst 0,%0" :: "r"(p));
		p += CACHELINESIZE;
	} while ((l -= CACHELINESIZE) > 0);
	__asm __volatile ("sync");
	p = from;
	l = len;
	do {
		__asm __volatile ("icbi 0,%0" :: "r"(p));
		p += CACHELINESIZE;
	} while ((l -= CACHELINESIZE) > 0);
	__asm __volatile ("isync");
}

static __inline void
invdcache(void *from, int len)
{
	int l;
	char *p = from;

	len = len + (((u_int32_t) from) & (CACHELINESIZE - 1));
	l = len;

	do {
		__asm __volatile ("dcbi 0,%0" :: "r"(p));
		p += CACHELINESIZE;
	} while ((l -= CACHELINESIZE) > 0);
	__asm __volatile ("sync");
}

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