From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ovro.ovro.caltech.edu (ovro.ovro.caltech.edu [192.100.16.2]) by ozlabs.org (Postfix) with ESMTP id 92AA7B6F7C for ; Sat, 28 May 2011 06:33:53 +1000 (EST) Message-ID: <4DE00AA7.2040804@ovro.caltech.edu> Date: Fri, 27 May 2011 13:33:43 -0700 From: David Hawkins MIME-Version: 1.0 To: Bruce_Leonard@selinc.com Subject: Re: MPC8308 bursting question References: <4DDFB49D.8010104@ovro.caltech.edu> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Cc: linuxppc-dev@lists.ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Hi Bruce, >> Read my MPC8349EA UPM setup notes and see if you have used >> similar settings (I assume the local bus UPMs are similar): > > I found you paper interesting. I didn't have a problem with my UPM > settings, single beat reads and writes worked just fine, however it did > tickle my memory and helped me find what was wrong. Turns out that the > person who was responsible for the BAx/ORx registers for this chip select > had set the BI bit a long time ago, before we were contemplating doing > what we're currently doing. The code had been reviewed and signed off, so > in my back brain I was thinking everything there was good. > > When I read your paper, it mentioned the BI bit which got me to thinking. > Sure enough, when I looked it was set. Soon as I cleared that bit, my > burst transactions started working just fine. > > Thanks for the help. You're welcome. I'm glad it helped. Cheers, Dave