From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:53472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRPBv-0001uf-QJ for qemu-devel@nongnu.org; Tue, 31 May 2011 09:41:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QRPBq-0002wp-Er for qemu-devel@nongnu.org; Tue, 31 May 2011 09:41:03 -0400 Received: from adelie.canonical.com ([91.189.90.139]:60234) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRPBq-0002wl-7d for qemu-devel@nongnu.org; Tue, 31 May 2011 09:40:58 -0400 Received: from loganberry.canonical.com ([91.189.90.37]) by adelie.canonical.com with esmtp (Exim 4.71 #1 (Debian)) id 1QRPBo-0007zj-Ai for ; Tue, 31 May 2011 13:40:56 +0000 Received: from loganberry.canonical.com (localhost [127.0.0.1]) by loganberry.canonical.com (Postfix) with ESMTP id 4FA8A2E890D for ; Tue, 31 May 2011 13:40:56 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Date: Tue, 31 May 2011 13:35:14 -0000 From: Nathan Whitehorn <788697@bugs.launchpad.net> Sender: bounces@canonical.com References: <20110526160930.15535.57397.malonedeb@soybean.canonical.com> <20110526160931.15535.77446.malone@soybean.canonical.com> <589FAE95-5CD6-482C-83F3-AF1FF301D854@suse.de> <4DDEE33A.3080100@freebsd.org> Message-Id: <4DE4EE92.6070202@freebsd.org> Errors-To: bounces@canonical.com Subject: Re: [Qemu-devel] [Bug 788697] Re: [PowerPC] [patch] mtmsr does not preserve high bits of MSR Reply-To: Bug 788697 <788697@bugs.launchpad.net> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 05/26/11 18:47, agraf wrote: > On 27.05.2011, at 01:33, Nathan Whitehorn wrote: > >> On 05/26/11 11:45, agraf wrote: >>> On 26.05.2011, at 18:09, Nathan Whitehorn wrote: >>> >>>> ** Patch added: "mtmstr.diff" >>>> https://bugs.launchpad.net/bugs/788697/+attachment/2143748/+files/m= tmstr.diff >>>> >>>> -- >>>> You received this bug notification because you are a member of qemu- >>>> devel-ml, which is subscribed to QEMU. >>>> https://bugs.launchpad.net/bugs/788697 >>>> >>>> Title: >>>> [PowerPC] [patch] mtmsr does not preserve high bits of MSR >>>> >>>> Status in QEMU: >>>> New >>>> >>>> Bug description: >>>> The mtmsr instruction on 64-bit PPC does not preserve the high-order >>>> 32-bits of the MSR the way it is supposed to, instead setting them to >>>> 0, which takes 64-bit code out of 64-bit mode. There is some code th= at >>>> does the right thing, but it brokenly only preserves these bits when >>>> the thread is not in 64-bit mode (i.e. when it doesn't matter). The >>>> attached patch unconditionally enables this code when TARGET_PPC64 is >>>> set, per the ISA spec, which fixes early boot failures trying to sta= rt >>>> FreeBSD/powerpc64 under qemu. >>>> >>> Please send the patch as proper patch to the ML and CC me. >> What isn't proper about the patch? I'm happy to re-email it, but don't >> want things to be in the wrong format. >> -Nathan > The patch needs a patch description in its header and a subject line > (all of which are present in the bug, so it's a simple matter of > copy&paste). Basically at the end of the day, I should be able to save > the mail and "git am" on it and simply have it in my tree :). > > Also, does this get FreeBSD booting up to anything useful, so I can > verify it helps? OK, I'll send this one out to today. The other issue I'm having (aside = from our own bugs), is that SPR_PIR is not implemented for the POWER7 = target. The architecture manual claims it is implemented on all Book-3S = compliant CPUs, but it seems to be implemented sort of ad-hoc in = target-ppc.c (e.g. the 604, 620, and 7400 have it, but not the 750, 970, = or POWER7). -Nathan -- = You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/788697 Title: [PowerPC] [patch] mtmsr does not preserve high bits of MSR Status in QEMU: New Bug description: The mtmsr instruction on 64-bit PPC does not preserve the high-order 32-bits of the MSR the way it is supposed to, instead setting them to 0, which takes 64-bit code out of 64-bit mode. There is some code that does the right thing, but it brokenly only preserves these bits when the thread is not in 64-bit mode (i.e. when it doesn't matter). The attached patch unconditionally enables this code when TARGET_PPC64 is set, per the ISA spec, which fixes early boot failures trying to start FreeBSD/powerpc64 under qemu.