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Date: Sun, 05 Jun 2011 18:32:12 +0200
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
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Subject: Re: [Qemu-devel] Disable interrupts on Cortex M3 (lm3s6965evb)
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, Paul Brook <paul@codesourcery.com>

On 05/06/11 16:57, Peter Maydell wrote:
> On 5 June 2011 15:17, Sebastian Huber
> <sebastian.huber@embedded-brains.de> wrote:
>   
>> On 05/06/11 15:44, Peter Maydell wrote:
[...]
>>> (It looks suspiciously as if most of the v7M priority handling
>>> is simply missing from QEMU, ie you have bigger problems than
>>> can be fixed by a small patch like this...)
>>>       
>   
>> Yes, but the current behaviour is definitely not right.  Since the
>> PRIMASK is mapped to the I bit in the CPSR I guessed that this was the
>> right place to fix it.
>>     
> I agree that the current behaviour is not right. However, to fix
> this problem you need to work on a larger scale than attempting
> to apply two line patches which fix your particular use case.
>   

I agree, but you have to start somewhere.  What is "this problem"?  Is
that we have no execution priority (in the sense of the ARMv7
architecture, B1.3.2 Exceptions), but instead use a mapping to CPSR_I
and CPSR_F?