From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([140.186.70.92]:37354)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1QV62s-0001sI-PT
	for qemu-devel@nongnu.org; Fri, 10 Jun 2011 14:02:59 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1QV62r-00027v-BD
	for qemu-devel@nongnu.org; Fri, 10 Jun 2011 14:02:58 -0400
Received: from mail-gx0-f173.google.com ([209.85.161.173]:47629)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1QV62q-00027o-Hl
	for qemu-devel@nongnu.org; Fri, 10 Jun 2011 14:02:56 -0400
Received: by gxk26 with SMTP id 26so2495748gxk.4
	for <qemu-devel@nongnu.org>; Fri, 10 Jun 2011 11:02:55 -0700 (PDT)
Sender: Richard Henderson <rth7680@gmail.com>
Message-ID: <4DF25C4C.7000700@twiddle.net>
Date: Fri, 10 Jun 2011 11:02:52 -0700
From: Richard Henderson <rth@twiddle.net>
MIME-Version: 1.0
References: <1307616344-27161-1-git-send-email-batuzovk@ispras.ru>
	<1307616344-27161-6-git-send-email-batuzovk@ispras.ru>
In-Reply-To: <1307616344-27161-6-git-send-email-batuzovk@ispras.ru>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH v2 5/6] Do constant folding for
	shift	operations.
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Kirill Batuzov <batuzovk@ispras.ru>
Cc: qemu-devel@nongnu.org, zhur@ispras.ru

On 06/09/2011 03:45 AM, Kirill Batuzov wrote:
> +    case INDEX_op_shl_i32:
> +#if TCG_TARGET_REG_BITS == 64
> +        y &= 0xffffffff;
> +    case INDEX_op_shl_i64:
> +#endif
> +        return x << y;
> +
> +    case INDEX_op_shr_i32:
> +#if TCG_TARGET_REG_BITS == 64
> +        x &= 0xffffffff;
> +        y &= 0xffffffff;
> +    case INDEX_op_shr_i64:
> +#endif
> +        /* Assuming TCGArg to be unsigned */
> +        return x >> y;

Don't assume when you've got a uint64_t type readily available.

> +    case INDEX_op_sar_i32:
> +#if TCG_TARGET_REG_BITS == 64
> +        x &= 0xffffffff;
> +        y &= 0xffffffff;
> +#endif
> +        return (int32_t)x >> (int32_t)y;

Masks are redundant with the casts.

> +    case INDEX_op_rotr_i32:
> +#if TCG_TARGET_REG_BITS == 64
> +        x &= 0xffffffff;
> +        y &= 0xffffffff;
> +#endif
> +        x = (x << (32 - y)) | (x >> y);

Have you looked to see if this gets recognized as a rotate
by the compiler?  I suspect that it will if you use a cast
to uint32_t here, but not if it is left as a 64-bit TCGArg.

> +#if TCG_TARGET_REG_BITS == 64
> +    case INDEX_op_rotl_i64:
> +        x = (x << y) | (x >> (64 - y));
> +        return x;
> +#endif

Likewise it's probably best to cast to uint64_t here.


r~