Hi Jingoo,

On 06/17/2011 03:01 PM, Jingoo Han wrote:
> This patch changes clock name for FIMD from "fimd" to "lcd".
> 
> Signed-off-by: Jingoo Han<jg1.han@samsung.com>
> ---
>   arch/arm/mach-exynos4/clock.c |    4 ++--
>   1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
> index 871f9d5..12e6853 100644
> --- a/arch/arm/mach-exynos4/clock.c
> +++ b/arch/arm/mach-exynos4/clock.c
> @@ -433,12 +433,12 @@ static struct clk init_clocks_off[] = {
>   		.enable		= exynos4_clk_ip_cam_ctrl,
>   		.ctrlbit	= (1<<  3),
>   	}, {
> -		.name		= "fimd",
> +		.name		= "lcd",
>   		.id		= 0,
>   		.enable		= exynos4_clk_ip_lcd0_ctrl,

I think we're inevitably heading to disaster with this kind of implicit
clocks mapping across various SoCs. It is getting harder to figure out
what's going on with every new SoC support added.  
The "fimd" clock in this case (exynos4) is not really a HCLK clock, like,
for instance, in case of s5pv210. But after this patch they would both be 
named "lcd". You cannot set frequency on "fimd" clock, it is only
for gating the bus clock to the LCD controller, right ? Whereas "lcd"
indicates HCLK on s5pv210 and can also be used to generate the LCD pixel
clock.
I know you are not going to use "lcd" clock in the driver for setting up
the pixel clock frequency on exynos4 but it's all confusing this way.

I dug in the datasheets and it looks like the LCD controller's IP main
(bus) clock is named HCLK there and "lcd" throughout the code.

          | LCD controller    |                            |
          | (IP core) clock   | LCD pixel clock            |
----------+------------------------+-----------------------+
s3c2440   |  HCLK (lcd)       | x  |  N/A ?                |
----------+------------------------+-----------------------+
s3c6410   |  HCLK (lcd)       | x  |  LCD                  |
----------+------------------------+-----------------------+
s5pc100   |  HCLK (lcd)       | x  |  SCLK_LCD  (sclk_lcd) |
----------+------------------------+-----------------------+
s5pv210   |  HCLK(_DSYS) (lcd)| x  |  SCLK_FIMD (sclk_fimd)|
----------+-----------------------+-----------------------+
exynos4   |  ?                | -  |  SCLK_FIMD?(sclk_fimd)|
----------+------------------------+-----------------------+

I think we could try to create two clock connection ids to the 
framebuffer device in the first place, e.g. "bus_ck", "pix_ck".
And then think about how handle that in the driver.

But this requires conversion to the omap-style clock registration
method, something like in the attached patch. The patch is only
for s5pv210 and and compile tested only as I didn't have any board
to test it here.
It's based on for-next branch at http://tinyurl.com/6yzravy
I think there might be more issues to convert the old s3c24xx
platforms, nevertheless the attached patch should not affect them.

--
Regards,
Sylwester