From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:59659) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QcfBk-0000Nd-GR for qemu-devel@nongnu.org; Fri, 01 Jul 2011 10:59:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QcfBh-0007EA-T5 for qemu-devel@nongnu.org; Fri, 01 Jul 2011 10:59:24 -0400 Received: from mel.act-europe.fr ([194.98.77.210]:39641) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QcfBh-0007De-CW for qemu-devel@nongnu.org; Fri, 01 Jul 2011 10:59:21 -0400 Message-ID: <4E0DE0C3.1030906@adacore.com> Date: Fri, 01 Jul 2011 16:59:15 +0200 From: Fabien Chouteau MIME-Version: 1.0 References: <1309180555-3942-1-git-send-email-chouteau@adacore.com> <20110627112807.22346e82@schlenkerla.am.freescale.net> <4E098E23.3040605@adacore.com> <20110628112008.31cf6237@schlenkerla.am.freescale.net> <4E0C32FB.40302@adacore.com> <20110630111745.7c544a06@schlenkerla.am.freescale.net> <86AF921C-3FD1-409A-ACFD-EEEA23BBE130@suse.de> <20110630164630.2bd57166@schlenkerla.am.freescale.net> <10F3D94F-5B79-4041-BFE7-58681B7E89CB@suse.de> <20110630171147.76eef3fc@schlenkerla.am.freescale.net> <9B335790-A8DA-4545-8746-F66B1B258FBF@suse.de> <20110630172345.36994f31@schlenkerla.am.freescale.net> <20110630173211.33924c99@schlenkerla.am.freescale.net> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] Add e500 instructions dcblc, dcbtls and dcbtstl as no-op List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Scott Wood , qemu-devel@nongnu.org On 01/07/2011 00:38, Alexander Graf wrote: > > On 01.07.2011, at 00:32, Scott Wood wrote: > >> On Fri, 1 Jul 2011 00:28:19 +0200 >> Alexander Graf wrote: >> >>> >>> On 01.07.2011, at 00:23, Scott Wood wrote: >>> >>>> On Fri, 1 Jul 2011 00:18:22 +0200 >>>> Alexander Graf wrote: >>>> >>>>> >>>>> On 01.07.2011, at 00:11, Scott Wood wrote: >>>>> >>>>>> Almost, but what if we have write permission but not read? >>>>> >>>>> How would you write back data from a cache line when you haven't read it earlier? >>>> >>>> The CPU can read it. The program can't. >>> >>> Hrm. We can always just call the check manually and trigger the respective interrupt :). >> >> Yep. A little trickier, but doable. >> >>>>>> but what about a race with DMA from the I/O thread? >>>>> >>>>> That'd simply be broken, but I don't quite see how it wouldn't with real hardware either :). >>>> >>>> Real hardware doesn't generate a load/store sequence that the program didn't >>>> ask for -- where's the breakage? >>> >>> Real hardware flushes whatever contents are in that cache line to RAM, no? So it would collide with the DMA just as much. Or am I missing something? >> >> If the DMA happens after the cache line is fetched, it'll be flushed, >> whether locked or not. But that's different from losing some of what the >> device wrote. > > Ah, so DMA flushes even locked cache lines? Then it makes sense. Well, I guess the best choice here really is to merely do a manual storage protection check and be done with it. > Well, this is far beyond the scope of my knowledge of e500 and the current patch is sufficient for me, so I will let you implement this if you want to... -- Fabien Chouteau