diff for duplicates of <4E2589C8.8010604@firmworks.com> diff --git a/a/1.txt b/N1/1.txt index bace24e..10d4196 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -15,7 +15,7 @@ On 7/19/2011 10:24 AM, Haojian Zhuang wrote: > While everything moving to DT in ARCH-MMP, original ttc_dkb.c and brownstone.c > will be abandoned. > -> Signed-off-by: Haojian Zhuang<haojian.zhuang@marvell.com> +> Signed-off-by: Haojian Zhuang<haojian.zhuang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org> > --- > .../devicetree/bindings/arm/marvell/boards.txt | 7 + > arch/arm/boot/dts/mmp2-brownstone.dts | 242 ++++++++++++++++++++ @@ -64,7 +64,7 @@ On 7/19/2011 10:24 AM, Haojian Zhuang wrote: > + linux,stdout-path =&uart2; > + }; > + -> + soc at d4000000 { +> + soc@d4000000 { > + compatible = "mrvl,mmp2", "mrvl,armada610", "simple-bus"; > + device_type = "soc"; @@ -90,7 +90,7 @@ addressing semantics of that kind of bus. See below for an exploration of how that might work, in the comments for the ttc-dkb "soc" node. > + -> + mmp_intc: interrupt-controller at d4282000 { +> + mmp_intc: interrupt-controller@d4282000 { > + compatible = "mrvl,mmp-intc"; > + #address-cells =<1>; > + #size-cells =<1>; @@ -110,7 +110,7 @@ the interrupt controller is not intended to have child nodes. > + intc-enable-mask =<0x20>; > + }; > + -> + mux_intc4: interrupt-controller at d4282150 { +> + mux_intc4: interrupt-controller@d4282150 { > + compatible = "mrvl,mux-intc"; > + #address-cells =<1>; > + #size-cells =<1>; @@ -127,7 +127,7 @@ the interrupt controller is not intended to have child nodes. > + intc-mfp-edge =<0xd401e2c4 1>; > + }; > + -> + mux_intc5: interrupt-controller at d4282154 { +> + mux_intc5: interrupt-controller@d4282154 { > + compatible = "mrvl,mux-intc"; > + #address-cells =<1>; > + #size-cells =<1>; @@ -145,7 +145,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + intc-mask =<0x16c>; > + }; > + -> + mux_intc9: interrupt-controller at d4282180 { +> + mux_intc9: interrupt-controller@d4282180 { > + compatible = "mrvl,mux-intc"; > + #address-cells =<1>; > + #size-cells =<1>; @@ -160,7 +160,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + intc-mask =<0x17c>; > + }; > + -> + mux_intc17: interrupt-controller at d4282158 { +> + mux_intc17: interrupt-controller@d4282158 { > + compatible = "mrvl,mux-intc"; > + #address-cells =<1>; > + #size-cells =<1>; @@ -175,7 +175,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + intc-mask =<0x170>; > + }; > + -> + mux_intc35: interrupt-controller at d428215c { +> + mux_intc35: interrupt-controller@d428215c { > + compatible = "mrvl,mux-intc"; > + #address-cells =<1>; > + #size-cells =<1>; @@ -190,7 +190,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + intc-mask =<0x174>; > + }; > + -> + mux_intc51: interrupt-controller at d4282160 { +> + mux_intc51: interrupt-controller@d4282160 { > + compatible = "mrvl,mux-intc"; > + #address-cells =<1>; > + #size-cells =<1>; @@ -205,7 +205,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + intc-mask =<0x178>; > + }; > + -> + mux_intc55: interrupt-controller at d4282188 { +> + mux_intc55: interrupt-controller@d4282188 { > + compatible = "mrvl,mux-intc"; > + #address-cells =<1>; > + #size-cells =<1>; @@ -220,7 +220,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + intc-mask =<0x184>; > + }; > + -> + i2c0: i2c at d4011000 { +> + i2c0: i2c@d4011000 { > + compatible = "mrvl,pxa255-i2c"; > + #address-cells =<1>; > + #size-cells =<0>; @@ -231,7 +231,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + interrupt-parent =<&mmp_intc>; > + }; > + -> + i2c1: i2c at d4031000 { +> + i2c1: i2c@d4031000 { > + compatible = "mrvl,pxa255-i2c"; > + reg =<0xd4031000 0x60>; > + i2c-polling =<0>; @@ -240,7 +240,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + interrupt-parent =<&mux_intc17>; > + }; > + -> + i2c2: i2c at d4032000 { +> + i2c2: i2c@d4032000 { > + compatible = "mrvl,pxa255-i2c"; > + reg =<0xd4032000 0x60>; > + i2c-polling =<0>; @@ -249,7 +249,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + interrupt-parent =<&mux_intc17>; > + }; > + -> + i2c3: i2c at d4033000 { +> + i2c3: i2c@d4033000 { > + compatible = "mrvl,pxa255-i2c"; > + reg =<0xd4033000 0x60>; > + i2c-polling =<0>; @@ -258,7 +258,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + interrupt-parent =<&mux_intc17>; > + }; > + -> + i2c4: i2c at d4033800 { +> + i2c4: i2c@d4033800 { > + compatible = "mrvl,pxa255-i2c"; > + reg =<0xd4033800 0x60>; > + i2c-polling =<0>; @@ -267,7 +267,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + interrupt-parent =<&mux_intc17>; > + }; > + -> + i2c5: i2c at d4034000 { +> + i2c5: i2c@d4034000 { > + compatible = "mrvl,pxa255-i2c"; > + reg =<0xd4034000 0x60>; > + i2c-polling =<0>; @@ -276,7 +276,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + interrupt-parent =<&mux_intc17>; > + }; > + -> + uart0: uart at d4030000 { +> + uart0: uart@d4030000 { > + compatible = "mrvl,pxa270-serial"; > + reg =<0xd4030000 0x1000>; > + reg-shift =<2>; @@ -286,7 +286,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + current-speed =<115200>; > + }; > + -> + uart1: uart at d4017000 { +> + uart1: uart@d4017000 { > + compatible = "mrvl,pxa270-serial"; > + reg =<0xd4017000 0x1000>; > + reg-shift =<2>; @@ -296,7 +296,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + current-speed =<115200>; > + }; > + -> + uart2: uart at d4018000 { +> + uart2: uart@d4018000 { > + compatible = "mrvl,pxa270-serial"; > + reg =<0xd4018000 0x1000>; > + reg-shift =<2>; @@ -306,7 +306,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + current-speed =<38400>; > + }; > + -> + uart3: uart at d4016000 { +> + uart3: uart@d4016000 { > + compatible = "mrvl,pxa270-serial"; > + reg =<0xd4016000 0x1000>; > + reg-shift =<2>; @@ -340,7 +340,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + linux,stdout-path =&uart0; > + }; > + -> + soc at d4000000 { +> + soc@d4000000 { > + compatible = "mrvl,pxa910", "simple-bus"; > + device_type = "soc"; > + #address-cells =<1>; @@ -355,20 +355,20 @@ better to do a proper translation here, instead of just passing the child addresses through. To fully express the APB/AXI structure, you could do it this way: -soc at d4000000 { +soc@d4000000 { compatible = "mrvl,pxa910", "simple-bus"; #address-cells =<2>; /* first cell: 0 for APB, 1 for AXI */ #size-cells =<1>; ranges =<0 0 0xd4000000 0x00200000 /* APB */ 0 1 0xd4200000 0x00200000>; /* AXI */ - mmp_intc: interrupt-controller at 1,82000 + mmp_intc: interrupt-controller@1,82000 reg = <1 0x82000 0x400>; with similar address modifications for other children. > + -> + mmp_intc: interrupt-controller at d4282000 { +> + mmp_intc: interrupt-controller@d4282000 { > + compatible = "mrvl,mmp-intc"; > + #address-cells =<1>; > + #size-cells =<1>; @@ -385,7 +385,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + intc-enable-mask =<0x51>; > + }; > + -> + i2c0: i2c at d4011000 { +> + i2c0: i2c@d4011000 { > + compatible = "mrvl,pxa255-i2c"; > + #address-cells =<1>; > + #size-cells =<0>; @@ -396,7 +396,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + interrupt-parent =<&mmp_intc>; > + }; > + -> + i2c1: i2c at d4037000 { +> + i2c1: i2c@d4037000 { > + compatible = "mrvl,pxa255-i2c"; > + reg =<0xd4037000 0x60>; > + i2c-polling =<0>; @@ -405,7 +405,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + interrupt-parent =<&mmp_intc>; > + }; > + -> + uart0: uart at d4017000 { +> + uart0: uart@d4017000 { > + compatible = "mrvl,pxa270-serial"; > + reg =<0xd4017000 0x1000>; > + reg-shift =<2>; @@ -415,7 +415,7 @@ Should not have #address-cells and #size-cells, as previously explained. > + current-speed =<115200>; > + }; > + -> + uart1: uart at d4018000 { +> + uart1: uart@d4018000 { > + compatible = "mrvl,pxa270-serial"; > + reg =<0xd4018000 0x1000>; > + reg-shift =<2>; diff --git a/a/content_digest b/N1/content_digest index 797741b..7e90adb 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,10 +3,18 @@ "ref\01311042290-20253-2-git-send-email-haojian.zhuang@marvell.com\0" "ref\01311042290-20253-3-git-send-email-haojian.zhuang@marvell.com\0" "ref\01311042290-20253-4-git-send-email-haojian.zhuang@marvell.com\0" - "From\0wmb@firmworks.com (Mitch Bradley)\0" - "Subject\0[PATCH 3/7] ARM: mmp: support DT on both dkb and brownstone\0" + "ref\01311042290-20253-4-git-send-email-haojian.zhuang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org\0" + "From\0Mitch Bradley <wmb-D5eQfiDGL7eakBO8gow8eQ@public.gmane.org>\0" + "Subject\0Re: [PATCH 3/7] ARM: mmp: support DT on both dkb and brownstone\0" "Date\0Tue, 19 Jul 2011 21:42:32 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Haojian Zhuang <haojian.zhuang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>\0" + "Cc\0eric.y.miao-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" + devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org + ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org + khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org + linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + " alan-VuQAYsv1563Yd54FQh9/CA@public.gmane.org\0" "\00:1\0" "b\0" "Thanks for doing this work. I'm currently working on a One Laptop Per \n" @@ -26,7 +34,7 @@ "> While everything moving to DT in ARCH-MMP, original ttc_dkb.c and brownstone.c\n" "> will be abandoned.\n" ">\n" - "> Signed-off-by: Haojian Zhuang<haojian.zhuang@marvell.com>\n" + "> Signed-off-by: Haojian Zhuang<haojian.zhuang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>\n" "> ---\n" "> .../devicetree/bindings/arm/marvell/boards.txt | 7 +\n" "> arch/arm/boot/dts/mmp2-brownstone.dts | 242 ++++++++++++++++++++\n" @@ -75,7 +83,7 @@ "> +\t\tlinux,stdout-path =&uart2;\n" "> +\t};\n" "> +\n" - "> +\tsoc at d4000000 {\n" + "> +\tsoc@d4000000 {\n" "> +\t\tcompatible = \"mrvl,mmp2\", \"mrvl,armada610\", \"simple-bus\";\n" "> +\t\tdevice_type = \"soc\";\n" "\n" @@ -101,7 +109,7 @@ "of how that might work, in the comments for the ttc-dkb \"soc\" node.\n" "\n" "> +\n" - "> +\t\tmmp_intc: interrupt-controller at d4282000 {\n" + "> +\t\tmmp_intc: interrupt-controller@d4282000 {\n" "> +\t\t\tcompatible = \"mrvl,mmp-intc\";\n" "> +\t\t\t#address-cells =<1>;\n" "> +\t\t\t#size-cells =<1>;\n" @@ -121,7 +129,7 @@ "> +\t\t\tintc-enable-mask =<0x20>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmux_intc4: interrupt-controller at d4282150 {\n" + "> +\t\tmux_intc4: interrupt-controller@d4282150 {\n" "> +\t\t\tcompatible = \"mrvl,mux-intc\";\n" "> +\t\t\t#address-cells =<1>;\n" "> +\t\t\t#size-cells =<1>;\n" @@ -138,7 +146,7 @@ "> +\t\t\tintc-mfp-edge =<0xd401e2c4 1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmux_intc5: interrupt-controller at d4282154 {\n" + "> +\t\tmux_intc5: interrupt-controller@d4282154 {\n" "> +\t\t\tcompatible = \"mrvl,mux-intc\";\n" "> +\t\t\t#address-cells =<1>;\n" "> +\t\t\t#size-cells =<1>;\n" @@ -156,7 +164,7 @@ "> +\t\t\tintc-mask =<0x16c>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmux_intc9: interrupt-controller at d4282180 {\n" + "> +\t\tmux_intc9: interrupt-controller@d4282180 {\n" "> +\t\t\tcompatible = \"mrvl,mux-intc\";\n" "> +\t\t\t#address-cells =<1>;\n" "> +\t\t\t#size-cells =<1>;\n" @@ -171,7 +179,7 @@ "> +\t\t\tintc-mask =<0x17c>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmux_intc17: interrupt-controller at d4282158 {\n" + "> +\t\tmux_intc17: interrupt-controller@d4282158 {\n" "> +\t\t\tcompatible = \"mrvl,mux-intc\";\n" "> +\t\t\t#address-cells =<1>;\n" "> +\t\t\t#size-cells =<1>;\n" @@ -186,7 +194,7 @@ "> +\t\t\tintc-mask =<0x170>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmux_intc35: interrupt-controller at d428215c {\n" + "> +\t\tmux_intc35: interrupt-controller@d428215c {\n" "> +\t\t\tcompatible = \"mrvl,mux-intc\";\n" "> +\t\t\t#address-cells =<1>;\n" "> +\t\t\t#size-cells =<1>;\n" @@ -201,7 +209,7 @@ "> +\t\t\tintc-mask =<0x174>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmux_intc51: interrupt-controller at d4282160 {\n" + "> +\t\tmux_intc51: interrupt-controller@d4282160 {\n" "> +\t\t\tcompatible = \"mrvl,mux-intc\";\n" "> +\t\t\t#address-cells =<1>;\n" "> +\t\t\t#size-cells =<1>;\n" @@ -216,7 +224,7 @@ "> +\t\t\tintc-mask =<0x178>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmux_intc55: interrupt-controller at d4282188 {\n" + "> +\t\tmux_intc55: interrupt-controller@d4282188 {\n" "> +\t\t\tcompatible = \"mrvl,mux-intc\";\n" "> +\t\t\t#address-cells =<1>;\n" "> +\t\t\t#size-cells =<1>;\n" @@ -231,7 +239,7 @@ "> +\t\t\tintc-mask =<0x184>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c0: i2c at d4011000 {\n" + "> +\t\ti2c0: i2c@d4011000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa255-i2c\";\n" "> +\t\t\t#address-cells =<1>;\n" "> +\t\t\t#size-cells =<0>;\n" @@ -242,7 +250,7 @@ "> +\t\t\tinterrupt-parent =<&mmp_intc>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c1: i2c at d4031000 {\n" + "> +\t\ti2c1: i2c@d4031000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa255-i2c\";\n" "> +\t\t\treg =<0xd4031000 0x60>;\n" "> +\t\t\ti2c-polling =<0>;\n" @@ -251,7 +259,7 @@ "> +\t\t\tinterrupt-parent =<&mux_intc17>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c2: i2c at d4032000 {\n" + "> +\t\ti2c2: i2c@d4032000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa255-i2c\";\n" "> +\t\t\treg =<0xd4032000 0x60>;\n" "> +\t\t\ti2c-polling =<0>;\n" @@ -260,7 +268,7 @@ "> +\t\t\tinterrupt-parent =<&mux_intc17>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c3: i2c at d4033000 {\n" + "> +\t\ti2c3: i2c@d4033000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa255-i2c\";\n" "> +\t\t\treg =<0xd4033000 0x60>;\n" "> +\t\t\ti2c-polling =<0>;\n" @@ -269,7 +277,7 @@ "> +\t\t\tinterrupt-parent =<&mux_intc17>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c4: i2c at d4033800 {\n" + "> +\t\ti2c4: i2c@d4033800 {\n" "> +\t\t\tcompatible = \"mrvl,pxa255-i2c\";\n" "> +\t\t\treg =<0xd4033800 0x60>;\n" "> +\t\t\ti2c-polling =<0>;\n" @@ -278,7 +286,7 @@ "> +\t\t\tinterrupt-parent =<&mux_intc17>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c5: i2c at d4034000 {\n" + "> +\t\ti2c5: i2c@d4034000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa255-i2c\";\n" "> +\t\t\treg =<0xd4034000 0x60>;\n" "> +\t\t\ti2c-polling =<0>;\n" @@ -287,7 +295,7 @@ "> +\t\t\tinterrupt-parent =<&mux_intc17>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: uart at d4030000 {\n" + "> +\t\tuart0: uart@d4030000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa270-serial\";\n" "> +\t\t\treg =<0xd4030000 0x1000>;\n" "> +\t\t\treg-shift =<2>;\n" @@ -297,7 +305,7 @@ "> +\t\t\tcurrent-speed =<115200>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart1: uart at d4017000 {\n" + "> +\t\tuart1: uart@d4017000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa270-serial\";\n" "> +\t\t\treg =<0xd4017000 0x1000>;\n" "> +\t\t\treg-shift =<2>;\n" @@ -307,7 +315,7 @@ "> +\t\t\tcurrent-speed =<115200>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart2: uart at d4018000 {\n" + "> +\t\tuart2: uart@d4018000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa270-serial\";\n" "> +\t\t\treg =<0xd4018000 0x1000>;\n" "> +\t\t\treg-shift =<2>;\n" @@ -317,7 +325,7 @@ "> +\t\t\tcurrent-speed =<38400>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart3: uart at d4016000 {\n" + "> +\t\tuart3: uart@d4016000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa270-serial\";\n" "> +\t\t\treg =<0xd4016000 0x1000>;\n" "> +\t\t\treg-shift =<2>;\n" @@ -351,7 +359,7 @@ "> +\t\tlinux,stdout-path =&uart0;\n" "> +\t};\n" "> +\n" - "> +\tsoc at d4000000 {\n" + "> +\tsoc@d4000000 {\n" "> +\t\tcompatible = \"mrvl,pxa910\", \"simple-bus\";\n" "> +\t\tdevice_type = \"soc\";\n" "> +\t\t#address-cells =<1>;\n" @@ -366,20 +374,20 @@ "child addresses through. To fully express the APB/AXI structure, you \n" "could do it this way:\n" "\n" - "soc at d4000000 {\n" + "soc@d4000000 {\n" "\tcompatible = \"mrvl,pxa910\", \"simple-bus\";\n" "\t#address-cells =<2>; /* first cell: 0 for APB, 1 for AXI */\n" "\t#size-cells =<1>;\n" "\tranges =<0 0 0xd4000000 0x00200000\t /* APB */\n" "\t\t 0 1 0xd4200000 0x00200000>;\t/* AXI */\n" "\n" - " mmp_intc: interrupt-controller at 1,82000\n" + " mmp_intc: interrupt-controller@1,82000\n" " reg = <1 0x82000 0x400>;\n" "\n" "with similar address modifications for other children.\n" "\n" "> +\n" - "> +\t\tmmp_intc: interrupt-controller at d4282000 {\n" + "> +\t\tmmp_intc: interrupt-controller@d4282000 {\n" "> +\t\t\tcompatible = \"mrvl,mmp-intc\";\n" "> +\t\t\t#address-cells =<1>;\n" "> +\t\t\t#size-cells =<1>;\n" @@ -396,7 +404,7 @@ "> +\t\t\tintc-enable-mask =<0x51>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c0: i2c at d4011000 {\n" + "> +\t\ti2c0: i2c@d4011000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa255-i2c\";\n" "> +\t\t\t#address-cells =<1>;\n" "> +\t\t\t#size-cells =<0>;\n" @@ -407,7 +415,7 @@ "> +\t\t\tinterrupt-parent =<&mmp_intc>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c1: i2c at d4037000 {\n" + "> +\t\ti2c1: i2c@d4037000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa255-i2c\";\n" "> +\t\t\treg =<0xd4037000 0x60>;\n" "> +\t\t\ti2c-polling =<0>;\n" @@ -416,7 +424,7 @@ "> +\t\t\tinterrupt-parent =<&mmp_intc>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: uart at d4017000 {\n" + "> +\t\tuart0: uart@d4017000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa270-serial\";\n" "> +\t\t\treg =<0xd4017000 0x1000>;\n" "> +\t\t\treg-shift =<2>;\n" @@ -426,7 +434,7 @@ "> +\t\t\tcurrent-speed =<115200>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart1: uart at d4018000 {\n" + "> +\t\tuart1: uart@d4018000 {\n" "> +\t\t\tcompatible = \"mrvl,pxa270-serial\";\n" "> +\t\t\treg =<0xd4018000 0x1000>;\n" "> +\t\t\treg-shift =<2>;\n" @@ -622,4 +630,4 @@ "> +MACHINE_END\n" > +#endif -82a25e6030834fed626265def26840d1d17c37ab9604c8b0f5892e5c2d55db0b +885ee60786b3a048bdd5ab8ca2ea23c71eb00285cbd101902eee127ab5017b65
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