From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:58180) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QpMsm-0002NP-02 for qemu-devel@nongnu.org; Fri, 05 Aug 2011 12:04:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QpMsk-0007lK-Js for qemu-devel@nongnu.org; Fri, 05 Aug 2011 12:04:19 -0400 Received: from mail-qw0-f45.google.com ([209.85.216.45]:57799) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QpMsk-0007lF-ET for qemu-devel@nongnu.org; Fri, 05 Aug 2011 12:04:18 -0400 Received: by qwj8 with SMTP id 8so241559qwj.4 for ; Fri, 05 Aug 2011 09:04:17 -0700 (PDT) Sender: Richard Henderson Message-ID: <4E3C147F.6070905@twiddle.net> Date: Fri, 05 Aug 2011 09:04:15 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1311527469-12963-1-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1311527469-12963-1-git-send-email-jcmvbkbc@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 00/31] target-xtensa: new target architecture List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Max Filippov Cc: qemu-devel@nongnu.org On 07/24/2011 10:10 AM, Max Filippov wrote: > This series adds support for Tensilica Xtensa target. > Port status: Linux for DC232B works in the qemu. > Not implemented xtensa options: MAC16, floating point coprocessor, > boolean option, cache option, debug option. > > v1 -> v2 changes: > - extract PS register and access control into separate patch; > - implement all memory protection options; > - GDB support. > > Max Filippov (31): > target-xtensa: add target stubs > target-xtensa: add target to the configure script > target-xtensa: implement disas_xtensa_insn > target-xtensa: implement narrow instructions > target-xtensa: implement RT0 group > target-xtensa: add sample board > target-xtensa: implement conditional jumps > target-xtensa: implement JX/RET0/CALLX > target-xtensa: add special and user registers > target-xtensa: implement RST3 group > target-xtensa: implement shifts (ST1 and RST1 groups) > target-xtensa: implement LSAI group > target-xtensa: mark reserved and TBD opcodes > target-xtensa: implement SYNC group > target-xtensa: implement CACHE group > target-xtensa: add PS register and access control > target-xtensa: implement exceptions > target-xtensa: implement RST2 group (32 bit mul/div/rem) > target-xtensa: implement windowed registers > target-xtensa: implement loop option > target-xtensa: implement extended L32R > target-xtensa: implement unaligned exception option > target-xtensa: implement SIMCALL > target-xtensa: implement interrupt option > target-xtensa: implement accurate window check > target-xtensa: implement CPENABLE and PRID SRs > target-xtensa: implement relocatable vectors > target-xtensa: add gdb support > target-xtensa: implement memory protection options > target-xtensa: add dc232b core and board > MAINTAINERS: add xtensa maintainer All parts: Reviewed-by: Richard Henderson I guess everything except the last couple of patches I'd already commented on in the last go-round. There's of course the conflict with the new Memory API that'll need to be resolved, but those are trivial changes. r~