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From: "H. Peter Anvin" <hpa@zytor.com>
To: Christoph Lameter <cl@linux.com>
Cc: Ingo Molnar <mingo@elte.hu>,
	linux-kernel@vger.kernel.org, Andi Kleen <ak@linux.intel.com>,
	"H. Peter Anvin" <hpa@linux.intel.com>
Subject: Re: [x86] Fix prefetch instruction
Date: Fri, 05 Aug 2011 13:13:37 -0700	[thread overview]
Message-ID: <4E3C4EF1.3040709@zytor.com> (raw)
In-Reply-To: <alpine.DEB.2.00.1108051116520.28580@router.home>

On 08/05/2011 09:18 AM, Christoph Lameter wrote:
> The prefetchnta instruction used for prefetching on x86 is a special instruction
> used for streaming that is usually used to avoid polluting the l2 and l3 caches.
> The cacheline will be evicted rapidly.
> 
> What we need is a prefetch that puts the cacheline in all levels of the cache hierachy instead.
> Change the instruction to do that.
> 
> Acked-by: Andi Kleen <ak@linux.intel.com>
> Signed-off-by: Christoph Lameter <cl@linux.com>
> 

Have you done any performance analysis on this versus the null case?  I
know there are some workloads where it helps, but if it hurts as many as
it helps...

	-hpa


  reply	other threads:[~2011-08-05 20:13 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-08-05 16:18 [x86] Fix prefetch instruction Christoph Lameter
2011-08-05 20:13 ` H. Peter Anvin [this message]
2011-08-05 21:10   ` Christoph Lameter
2011-08-05 21:22     ` H. Peter Anvin
2011-08-05 23:32       ` Christoph Lameter
2011-08-05 23:53         ` H. Peter Anvin

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