diff for duplicates of <4E5F5360.6060400@freescale.com> diff --git a/a/1.txt b/N1/1.txt index 6f07fa3..1c0dd47 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,39 +1,55 @@ -于 2011年08月25日 19:25, Matthieu CASTET 写道: +=E4=BA=8E 2011=E5=B9=B408=E6=9C=8825=E6=97=A5 19:25, Matthieu CASTET =E5=86= +=99=E9=81=93: > Hi, > -> LiuShuo a écrit : ->> 于 2011年08月23日 18:02, Matthieu CASTET 写道: ->>> LiuShuo a écrit : ->>>> 于 2011年08月19日 00:25, Scott Wood 写道: +> LiuShuo a =C3=A9crit : +>> =E4=BA=8E 2011=E5=B9=B408=E6=9C=8823=E6=97=A5 18:02, Matthieu CASTET =E5= +=86=99=E9=81=93: +>>> LiuShuo a =C3=A9crit : +>>>> =E4=BA=8E 2011=E5=B9=B408=E6=9C=8819=E6=97=A5 00:25, Scott Wood =E5=86= +=99=E9=81=93: >>>>> On 08/17/2011 09:33 PM, b35362@freescale.com wrote: >>>>>> From: Liu Shuo<b35362@freescale.com> >>>>>> ->>>>>> Freescale FCM controller has a 2K size limitation of buffer RAM. In order ->>>>>> to support the Nand flash chip whose page size is larger than 2K bytes, ->>>>>> we divide a page into multi-2K pages for MTD layer driver. In that case, ->>>>>> we force to set the page size to 2K bytes. We convert the page address of ->>>>>> MTD layer driver to a real page address in flash chips and a column index ->>>>>> in fsl_elbc driver. We can issue any column address by UA instruction of +>>>>>> Freescale FCM controller has a 2K size limitation of buffer RAM. I= +n order +>>>>>> to support the Nand flash chip whose page size is larger than 2K b= +ytes, +>>>>>> we divide a page into multi-2K pages for MTD layer driver. In that= + case, +>>>>>> we force to set the page size to 2K bytes. We convert the page add= +ress of +>>>>>> MTD layer driver to a real page address in flash chips and a colum= +n index +>>>>>> in fsl_elbc driver. We can issue any column address by UA instruct= +ion of >>>>>> elbc controller. >>>>>> ->>>>>> NOTE: Due to there is a limitation of 'Number of Partial Program Cycles in ->>>>>> the Same Page (NOP)', the flash chip which is supported by this workaround +>>>>>> NOTE: Due to there is a limitation of 'Number of Partial Program C= +ycles in +>>>>>> the Same Page (NOP)', the flash chip which is supported by this wo= +rkaround >>>>>> have to meet below conditions. >>>>>> 1. page size is not greater than 4KB >>>>>> 2. 1) if main area and spare area have independent NOPs: ->>>>>> main area NOP :>=3 ->>>>>> spare area NOP :>=2? +>>>>>> main area NOP :>=3D3 +>>>>>> spare area NOP :>=3D2? >>>>> How often are the NOPs split like this? >>>>> >>>>>> 2) if main area and spare area have a common NOP: ->>>>>> NOP :>=4 ->>>>> This depends on how the flash is used. If you treat it as a NOP1 flash ->>>>> (e.g. run ubifs rather than jffs2), then you need NOP2 for a 4K chip and ->>>>> NOP4 for an 8K chip. OTOH, if you would be making full use of NOP4 on a +>>>>>> NOP :>=3D4 +>>>>> This depends on how the flash is used. If you treat it as a NOP1 f= +lash +>>>>> (e.g. run ubifs rather than jffs2), then you need NOP2 for a 4K chi= +p and +>>>>> NOP4 for an 8K chip. OTOH, if you would be making full use of NOP4= + on a >>>>> real 2K chip, you'll need NOP8 for a 4K chip. >>>>> ->>>>> The NOP restrictions should be documented in the code itself, not just ->>>>> in the git changelog. Maybe print it to the console when this hack is +>>>>> The NOP restrictions should be documented in the code itself, not j= +ust +>>>>> in the git changelog. Maybe print it to the console when this hack= + is >>>>> used, along with the NOP value read from the ID. >>>> We can't read the NOP from the ID on any chip. Some chips don't >>>> give this infomation.(e.g. Micron MT29F4G08BAC) @@ -42,11 +58,13 @@ >> We can get the NOP info from datasheet, but can't get it by READID >> command in code. >> -> ok I was thinking the micron chip was a 4K nand. But it is an old 2K. Why do you +> ok I was thinking the micron chip was a 4K nand. But it is an old 2K. W= +hy do you > want NOP from it ? > > -> Also can you reply my question about the sequence you use when trying to read 4k +> Also can you reply my question about the sequence you use when trying t= +o read 4k > with one command. > > @@ -57,13 +75,14 @@ > Sorry for late reply. -After doing some tests, I found that the elbc controller can read/write +After doing some tests, I found that the elbc controller can read/write=20 4k with one command -if we insert a FIR_OP_NOP between first half reading/wring and second +if we insert a FIR_OP_NOP between first half reading/wring and second=20 half reading/writing.(delay for something ?) Read sequence : ------------------------------------------------------------------------------------------------------------------------ +-------------------------------------------------------------------------= +---------------------------------------------- first half : out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) | @@ -73,21 +92,23 @@ first half : (FIR_OP_RBW << FIR_OP4_SHIFT)); out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | - (NAND_CMD_READSTART << + (NAND_CMD_READSTART <<=20 FCR_CMD1_SHIFT)); second half : out_be32(&lbc->fir, - (FIR_OP_RB << FIR_OP1_SHIFT)); + (FIR_OP_RB << FIR_OP1_SHIFT)); =20 // FIR_OP0_SHIFT is FIR_OP_NOP ------------------------------------------------------------------------------------------------------------------------ +-------------------------------------------------------------------------= +---------------------------------------------- Write sequence : ------------------------------------------------------------------------------------------------------------------------ +-------------------------------------------------------------------------= +---------------------------------------------- first half: - fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | + fcr =3D (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) | (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT); @@ -103,7 +124,8 @@ second half: (FIR_OP_CM3 << FIR_OP2_SHIFT) | (FIR_OP_CW1 << FIR_OP3_SHIFT) | (FIR_OP_RS << FIR_OP4_SHIFT)); ------------------------------------------------------------------------------------------------------------------------ +-------------------------------------------------------------------------= +---------------------------------------------- I am going to try to finish it and send a new patch. diff --git a/a/content_digest b/N1/content_digest index b227457..d1cbf94 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -15,42 +15,58 @@ " linux-mtd@lists.infradead.org <linux-mtd@lists.infradead.org>\0" "\00:1\0" "b\0" - "\344\272\216 2011\345\271\26408\346\234\21025\346\227\245 19:25, Matthieu CASTET \345\206\231\351\201\223:\n" + "=E4=BA=8E 2011=E5=B9=B408=E6=9C=8825=E6=97=A5 19:25, Matthieu CASTET =E5=86=\n" + "=99=E9=81=93:\n" "> Hi,\n" ">\n" - "> LiuShuo a \303\251crit :\n" - ">> \344\272\216 2011\345\271\26408\346\234\21023\346\227\245 18:02, Matthieu CASTET \345\206\231\351\201\223:\n" - ">>> LiuShuo a \303\251crit :\n" - ">>>> \344\272\216 2011\345\271\26408\346\234\21019\346\227\245 00:25, Scott Wood \345\206\231\351\201\223:\n" + "> LiuShuo a =C3=A9crit :\n" + ">> =E4=BA=8E 2011=E5=B9=B408=E6=9C=8823=E6=97=A5 18:02, Matthieu CASTET =E5=\n" + "=86=99=E9=81=93:\n" + ">>> LiuShuo a =C3=A9crit :\n" + ">>>> =E4=BA=8E 2011=E5=B9=B408=E6=9C=8819=E6=97=A5 00:25, Scott Wood =E5=86=\n" + "=99=E9=81=93:\n" ">>>>> On 08/17/2011 09:33 PM, b35362@freescale.com wrote:\n" ">>>>>> From: Liu Shuo<b35362@freescale.com>\n" ">>>>>>\n" - ">>>>>> Freescale FCM controller has a 2K size limitation of buffer RAM. In order\n" - ">>>>>> to support the Nand flash chip whose page size is larger than 2K bytes,\n" - ">>>>>> we divide a page into multi-2K pages for MTD layer driver. In that case,\n" - ">>>>>> we force to set the page size to 2K bytes. We convert the page address of\n" - ">>>>>> MTD layer driver to a real page address in flash chips and a column index\n" - ">>>>>> in fsl_elbc driver. We can issue any column address by UA instruction of\n" + ">>>>>> Freescale FCM controller has a 2K size limitation of buffer RAM. I=\n" + "n order\n" + ">>>>>> to support the Nand flash chip whose page size is larger than 2K b=\n" + "ytes,\n" + ">>>>>> we divide a page into multi-2K pages for MTD layer driver. In that=\n" + " case,\n" + ">>>>>> we force to set the page size to 2K bytes. We convert the page add=\n" + "ress of\n" + ">>>>>> MTD layer driver to a real page address in flash chips and a colum=\n" + "n index\n" + ">>>>>> in fsl_elbc driver. We can issue any column address by UA instruct=\n" + "ion of\n" ">>>>>> elbc controller.\n" ">>>>>>\n" - ">>>>>> NOTE: Due to there is a limitation of 'Number of Partial Program Cycles in\n" - ">>>>>> the Same Page (NOP)', the flash chip which is supported by this workaround\n" + ">>>>>> NOTE: Due to there is a limitation of 'Number of Partial Program C=\n" + "ycles in\n" + ">>>>>> the Same Page (NOP)', the flash chip which is supported by this wo=\n" + "rkaround\n" ">>>>>> have to meet below conditions.\n" ">>>>>> \t1. page size is not greater than 4KB\n" ">>>>>> \t2.\t1) if main area and spare area have independent NOPs:\n" - ">>>>>> \t\t\t main area NOP :>=3\n" - ">>>>>> \t\t\t spare area NOP :>=2?\n" + ">>>>>> \t\t\t main area NOP :>=3D3\n" + ">>>>>> \t\t\t spare area NOP :>=3D2?\n" ">>>>> How often are the NOPs split like this?\n" ">>>>>\n" ">>>>>> \t\t2) if main area and spare area have a common NOP:\n" - ">>>>>> \t\t\t NOP :>=4\n" - ">>>>> This depends on how the flash is used. If you treat it as a NOP1 flash\n" - ">>>>> (e.g. run ubifs rather than jffs2), then you need NOP2 for a 4K chip and\n" - ">>>>> NOP4 for an 8K chip. OTOH, if you would be making full use of NOP4 on a\n" + ">>>>>> \t\t\t NOP :>=3D4\n" + ">>>>> This depends on how the flash is used. If you treat it as a NOP1 f=\n" + "lash\n" + ">>>>> (e.g. run ubifs rather than jffs2), then you need NOP2 for a 4K chi=\n" + "p and\n" + ">>>>> NOP4 for an 8K chip. OTOH, if you would be making full use of NOP4=\n" + " on a\n" ">>>>> real 2K chip, you'll need NOP8 for a 4K chip.\n" ">>>>>\n" - ">>>>> The NOP restrictions should be documented in the code itself, not just\n" - ">>>>> in the git changelog. Maybe print it to the console when this hack is\n" + ">>>>> The NOP restrictions should be documented in the code itself, not j=\n" + "ust\n" + ">>>>> in the git changelog. Maybe print it to the console when this hack=\n" + " is\n" ">>>>> used, along with the NOP value read from the ID.\n" ">>>> We can't read the NOP from the ID on any chip. Some chips don't\n" ">>>> give this infomation.(e.g. Micron MT29F4G08BAC)\n" @@ -59,11 +75,13 @@ ">> We can get the NOP info from datasheet, but can't get it by READID\n" ">> command in code.\n" ">>\n" - "> ok I was thinking the micron chip was a 4K nand. But it is an old 2K. Why do you\n" + "> ok I was thinking the micron chip was a 4K nand. But it is an old 2K. W=\n" + "hy do you\n" "> want NOP from it ?\n" ">\n" ">\n" - "> Also can you reply my question about the sequence you use when trying to read 4k\n" + "> Also can you reply my question about the sequence you use when trying t=\n" + "o read 4k\n" "> with one command.\n" ">\n" ">\n" @@ -74,13 +92,14 @@ ">\n" "Sorry for late reply.\n" "\n" - "After doing some tests, I found that the elbc controller can read/write \n" + "After doing some tests, I found that the elbc controller can read/write=20\n" "4k with one command\n" - "if we insert a FIR_OP_NOP between first half reading/wring and second \n" + "if we insert a FIR_OP_NOP between first half reading/wring and second=20\n" "half reading/writing.(delay for something ?)\n" "\n" "Read sequence :\n" - "-----------------------------------------------------------------------------------------------------------------------\n" + "-------------------------------------------------------------------------=\n" + "----------------------------------------------\n" "first half :\n" " out_be32(&lbc->fir,\n" " (FIR_OP_CM0 << FIR_OP0_SHIFT) |\n" @@ -90,21 +109,23 @@ " (FIR_OP_RBW << FIR_OP4_SHIFT));\n" "\n" " out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |\n" - " (NAND_CMD_READSTART << \n" + " (NAND_CMD_READSTART <<=20\n" "FCR_CMD1_SHIFT));\n" "\n" "second half :\n" " out_be32(&lbc->fir,\n" - " (FIR_OP_RB << FIR_OP1_SHIFT)); \n" + " (FIR_OP_RB << FIR_OP1_SHIFT)); =20\n" "// FIR_OP0_SHIFT is FIR_OP_NOP\n" - "-----------------------------------------------------------------------------------------------------------------------\n" + "-------------------------------------------------------------------------=\n" + "----------------------------------------------\n" "\n" "\n" "Write sequence :\n" - "-----------------------------------------------------------------------------------------------------------------------\n" + "-------------------------------------------------------------------------=\n" + "----------------------------------------------\n" "\n" "first half:\n" - " fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |\n" + " fcr =3D (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |\n" " (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) |\n" " (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);\n" "\n" @@ -120,11 +141,12 @@ " (FIR_OP_CM3 << FIR_OP2_SHIFT) |\n" " (FIR_OP_CW1 << FIR_OP3_SHIFT) |\n" " (FIR_OP_RS << FIR_OP4_SHIFT));\n" - "-----------------------------------------------------------------------------------------------------------------------\n" + "-------------------------------------------------------------------------=\n" + "----------------------------------------------\n" "\n" "I am going to try to finish it and send a new patch.\n" "\n" "\n" -LiuShuo -9f7010ba7f0de991436f724c8ac1bf627b5a0c2431ed82b353b5867144210cc0 +62c068e50e03c619c1e4bd25a16e6af3b7f50504644dafeb6a8f5e6ebf997f7d
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