From mboxrd@z Thu Jan 1 00:00:00 1970 From: Santosh Subject: Re: [PATCH 14/25] OMAP4: PM: Add CPUX OFF mode support Date: Fri, 09 Sep 2011 22:29:49 +0530 Message-ID: <4E6A4605.3050305@ti.com> References: <1315144466-9395-1-git-send-email-santosh.shilimkar@ti.com> <1315144466-9395-15-git-send-email-santosh.shilimkar@ti.com> <20110909080416.GF31581@S2100-06.ap.freescale.net> <4E69C9CF.6090709@ti.com> <20110909141321.GC32138@S2100-06.ap.freescale.net> <20110909152729.GG32138@S2100-06.ap.freescale.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-path: Received: from na3sys009aog125.obsmtp.com ([74.125.149.153]:53520 "EHLO na3sys009aog125.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758985Ab1IIRAA (ORCPT ); Fri, 9 Sep 2011 13:00:00 -0400 Received: by pzd13 with SMTP id 13so1234004pzd.23 for ; Fri, 09 Sep 2011 09:59:57 -0700 (PDT) In-Reply-To: <20110909152729.GG32138@S2100-06.ap.freescale.net> Sender: linux-omap-owner@vger.kernel.org List-Id: linux-omap@vger.kernel.org To: Shawn Guo Cc: khilman@ti.com, linux-omap@vger.kernel.org, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, rnayak@ti.com, Dave Martin On Friday 09 September 2011 08:57 PM, Shawn Guo wrote: > On Fri, Sep 09, 2011 at 07:41:08PM +0530, Shilimkar, Santosh wrote: >> On Fri, Sep 9, 2011 at 7:43 PM, Shawn Guo wrote: >>> On Fri, Sep 09, 2011 at 01:39:51PM +0530, Santosh wrote: >>>> On Friday 09 September 2011 01:34 PM, Shawn Guo wrote: >>>>> Hi Santosh, [...] >> #ifdef CONFIG_CACHE_L2X0 >> /* >> * Clean and invalidate the L2 cache. >> * Common cache-l2x0.c functions can't be used here since it >> * uses spinlocks. We are out of coherency here with data cache >> * disabled. The spinlock implementation uses exclusive load/store >> * instruction which can fail without data cache being enabled. >> * OMAP4 hardware doesn't support exclusive monitor which can >> * overcome exclusive access issue. Because of this, CPU can >> * lead to deadlock. >> */ >> l2x_clean_inv: >> bl omap4_get_sar_ram_base >> mov r8, r0 >> mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR >> ands r5, r5, #0x0f >> ldreq r0, [r8, #L2X0_SAVE_OFFSET0] >> ldrne r0, [r8, #L2X0_SAVE_OFFSET1] >> cmp r0, #3 >> bne do_WFI > > It looks like you are bypassing L2 clean and invalidate for cases > "1" and "2" here. But I really do not understand how you get r0 > back here. > The value which is passed in R0 is also stored in scratch patch memory and retrieved using L2X0_SAVE_OFFSET0. Simple :) Regards Santosh From mboxrd@z Thu Jan 1 00:00:00 1970 From: santosh.shilimkar@ti.com (Santosh) Date: Fri, 09 Sep 2011 22:29:49 +0530 Subject: [PATCH 14/25] OMAP4: PM: Add CPUX OFF mode support In-Reply-To: <20110909152729.GG32138@S2100-06.ap.freescale.net> References: <1315144466-9395-1-git-send-email-santosh.shilimkar@ti.com> <1315144466-9395-15-git-send-email-santosh.shilimkar@ti.com> <20110909080416.GF31581@S2100-06.ap.freescale.net> <4E69C9CF.6090709@ti.com> <20110909141321.GC32138@S2100-06.ap.freescale.net> <20110909152729.GG32138@S2100-06.ap.freescale.net> Message-ID: <4E6A4605.3050305@ti.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Friday 09 September 2011 08:57 PM, Shawn Guo wrote: > On Fri, Sep 09, 2011 at 07:41:08PM +0530, Shilimkar, Santosh wrote: >> On Fri, Sep 9, 2011 at 7:43 PM, Shawn Guo wrote: >>> On Fri, Sep 09, 2011 at 01:39:51PM +0530, Santosh wrote: >>>> On Friday 09 September 2011 01:34 PM, Shawn Guo wrote: >>>>> Hi Santosh, [...] >> #ifdef CONFIG_CACHE_L2X0 >> /* >> * Clean and invalidate the L2 cache. >> * Common cache-l2x0.c functions can't be used here since it >> * uses spinlocks. We are out of coherency here with data cache >> * disabled. The spinlock implementation uses exclusive load/store >> * instruction which can fail without data cache being enabled. >> * OMAP4 hardware doesn't support exclusive monitor which can >> * overcome exclusive access issue. Because of this, CPU can >> * lead to deadlock. >> */ >> l2x_clean_inv: >> bl omap4_get_sar_ram_base >> mov r8, r0 >> mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR >> ands r5, r5, #0x0f >> ldreq r0, [r8, #L2X0_SAVE_OFFSET0] >> ldrne r0, [r8, #L2X0_SAVE_OFFSET1] >> cmp r0, #3 >> bne do_WFI > > It looks like you are bypassing L2 clean and invalidate for cases > "1" and "2" here. But I really do not understand how you get r0 > back here. > The value which is passed in R0 is also stored in scratch patch memory and retrieved using L2X0_SAVE_OFFSET0. Simple :) Regards Santosh