From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:52404) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R3T2x-0006Cv-Gr for qemu-devel@nongnu.org; Tue, 13 Sep 2011 09:29:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R3T2s-0007Mv-Ht for qemu-devel@nongnu.org; Tue, 13 Sep 2011 09:29:07 -0400 Message-ID: <4E6F5A93.8000805@adacore.com> Date: Tue, 13 Sep 2011 15:28:51 +0200 From: Fabien Chouteau MIME-Version: 1.0 References: <1314865231-24433-1-git-send-email-chouteau@adacore.com> <7F526FE3-48CD-45BE-8135-94901C26121D@suse.de> <4E6782AC.9070603@adacore.com> <765F067E-9AD5-4626-8740-1E6FC3A7571F@suse.de> <4E69EC24.4030606@adacore.com> <57B05115-B9BC-4E06-BA27-F415B27B0E86@suse.de> <4E6A1440.9010201@adacore.com> <67C14AF0-B34A-43C8-B9FB-43270D929F87@suse.de> <4E6A212C.30709@adacore.com> <1C102E0E-5ACA-4457-997D-DE4FCAC1F625@suse.de> <4E6E4018.3020106@freescale.com> <4E6F5560.4000506@adacore.com> <4E6F55D8.20802@suse.de> <4E6F56F3.8070904@suse.de> In-Reply-To: <4E6F56F3.8070904@suse.de> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Qemu-ppc] [RESEND][PATCH] booke timers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Scott Wood , qemu-ppc@nongnu.org, "qemu-devel@nongnu.org Developers" On 13/09/2011 15:13, Alexander Graf wrote: > Alexander Graf wrote: >> Fabien Chouteau wrote: >> >>> On 12/09/2011 19:23, Scott Wood wrote: >>> >>> >>>> On 09/09/2011 09:58 AM, Alexander Graf wrote: >>>> >>>> >>>>> On 09.09.2011, at 16:22, Fabien Chouteau wrote: >>>>> >>>>> >>>>>> if the interrupt is already set and you clear TCR.DIE, the interrupt has to >>>>>> remain set. The only way to unset an interrupt is to clear the corresponding >>>>>> bit in TSR (currently in store_booke_tsr). >>>>>> >>>>>> >>>>> Are you sure? I see several things in the 2.06 spec: >>>>> >>>>> >>>> [snip] >>>> >>>> >>>>> To me that sounds as if the decrementer interrupt gets injected only >>>>> when TSR.DIS=1, TCR.DIE=1 and MSR.EE=1. Unsetting any of these bits >>>>> stops the interrupt from being delivered. >>>>> >>>>> Scott, can you please check up with the hardware guys if this is correct? >>>>> >>>>> >>>> This is how I've always understood it to work (assuming the interrupt >>>> hasn't already been delivered, of course). Fabien, do you have real >>>> hardware that you see behave the way you describe? >>>> >>>> >>>> >>> No I don't, it was just my understanding of Book-E documentation. I've tried >>> your solution (below) with VxWorks, and it works like a charm. >>> >>> static void booke_update_irq(CPUState *env) >>> { >>> ppc_set_irq(env, PPC_INTERRUPT_DECR, >>> (env->spr[SPR_BOOKE_TSR] & TSR_DIS >>> && env->spr[SPR_BOOKE_TCR] & TCR_DIE)); >>> >>> ppc_set_irq(env, PPC_INTERRUPT_WDT, >>> (env->spr[SPR_BOOKE_TSR] & TSR_WIS >>> && env->spr[SPR_BOOKE_TCR] & TCR_WIE)); >>> >>> ppc_set_irq(env, PPC_INTERRUPT_FIT, >>> (env->spr[SPR_BOOKE_TSR] & TSR_FIS >>> && env->spr[SPR_BOOKE_TCR] & TCR_FIE)); >>> } >>> >>> >> >> Awesome! Please also check on MSR.EE and send a new patch then :) >> > > Ah, the EE check is in target-ppc/helper.c:ppc_hw_interrupt. Very > confusing (and probably wrong because it could generate spurious > interrupts), but it should be enough for now. > That's what I was looking for... So we are good. -- Fabien Chouteau