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diff for duplicates of <4E70EB1F.4060000@gmail.com>

diff --git a/a/content_digest b/N1/content_digest
index 25c727e..556615f 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,10 +1,19 @@
  "ref\01316017900-19918-1-git-send-email-robherring2@gmail.com\0"
  "ref\01316017900-19918-6-git-send-email-robherring2@gmail.com\0"
  "ref\04E70E88E.4090503@arm.com\0"
- "From\0robherring2@gmail.com (Rob Herring)\0"
- "Subject\0[PATCH 5/5] ARM: gic: add OF based initialization\0"
+ "From\0Rob Herring <robherring2@gmail.com>\0"
+ "Subject\0Re: [PATCH 5/5] ARM: gic: add OF based initialization\0"
  "Date\0Wed, 14 Sep 2011 12:57:51 -0500\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Marc Zyngier <marc.zyngier@arm.com>\0"
+ "Cc\0linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>"
+  devicetree-discuss@lists.ozlabs.org <devicetree-discuss@lists.ozlabs.org>
+  linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>
+  grant.likely@secretlab.ca <grant.likely@secretlab.ca>
+  thomas.abraham@linaro.org <thomas.abraham@linaro.org>
+  jamie@jamieiles.com <jamie@jamieiles.com>
+  b-cousson@ti.com <b-cousson@ti.com>
+  shawn.guo@linaro.org <shawn.guo@linaro.org>
+ " Rob Herring <rob.herring@calxeda.com>\0"
  "\00:1\0"
  "b\0"
  "Marc,\n"
@@ -83,4 +92,4 @@
  "\n"
  Rob
 
-45c6eacfc94f42568c70212e44c16873508d1dda85b5cf2d3f710a76f1e8aabb
+481afa3e74ddefdca5c0a3689232142f3eb8483841f59a328340bb8679bf20ca

diff --git a/a/1.txt b/N2/1.txt
index 7c14b69..b867ef3 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -2,7 +2,7 @@ Marc,
 
 On 09/14/2011 12:46 PM, Marc Zyngier wrote:
 > On 14/09/11 17:31, Rob Herring wrote:
->> From: Rob Herring <rob.herring@calxeda.com>
+>> From: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
 >>
 >> This adds gic initialization using device tree data. The initialization
 >> functions are intended to be called by a generic OF interrupt
@@ -11,7 +11,7 @@ On 09/14/2011 12:46 PM, Marc Zyngier wrote:
 >> PPIs are handled using 3rd cell of interrupts properties to specify the cpu
 >> mask the PPI is assigned to.
 >>
->> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
+>> Signed-off-by: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
 >> ---
 >>  Documentation/devicetree/bindings/arm/gic.txt |   53 ++++++++++++++++++++++++
 >>  arch/arm/common/gic.c                         |   55 +++++++++++++++++++++++--
diff --git a/a/content_digest b/N2/content_digest
index 25c727e..a3ebb68 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -1,17 +1,22 @@
  "ref\01316017900-19918-1-git-send-email-robherring2@gmail.com\0"
  "ref\01316017900-19918-6-git-send-email-robherring2@gmail.com\0"
  "ref\04E70E88E.4090503@arm.com\0"
- "From\0robherring2@gmail.com (Rob Herring)\0"
- "Subject\0[PATCH 5/5] ARM: gic: add OF based initialization\0"
+ "ref\04E70E88E.4090503-5wv7dgnIgG8@public.gmane.org\0"
+ "From\0Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0"
+ "Subject\0Re: [PATCH 5/5] ARM: gic: add OF based initialization\0"
  "Date\0Wed, 14 Sep 2011 12:57:51 -0500\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>\0"
+ "Cc\0devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org <devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org>"
+  linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
+  Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
+ " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0"
  "\00:1\0"
  "b\0"
  "Marc,\n"
  "\n"
  "On 09/14/2011 12:46 PM, Marc Zyngier wrote:\n"
  "> On 14/09/11 17:31, Rob Herring wrote:\n"
- ">> From: Rob Herring <rob.herring@calxeda.com>\n"
+ ">> From: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>\n"
  ">>\n"
  ">> This adds gic initialization using device tree data. The initialization\n"
  ">> functions are intended to be called by a generic OF interrupt\n"
@@ -20,7 +25,7 @@
  ">> PPIs are handled using 3rd cell of interrupts properties to specify the cpu\n"
  ">> mask the PPI is assigned to.\n"
  ">>\n"
- ">> Signed-off-by: Rob Herring <rob.herring@calxeda.com>\n"
+ ">> Signed-off-by: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>\n"
  ">> ---\n"
  ">>  Documentation/devicetree/bindings/arm/gic.txt |   53 ++++++++++++++++++++++++\n"
  ">>  arch/arm/common/gic.c                         |   55 +++++++++++++++++++++++--\n"
@@ -83,4 +88,4 @@
  "\n"
  Rob
 
-45c6eacfc94f42568c70212e44c16873508d1dda85b5cf2d3f710a76f1e8aabb
+61314f8f0ebd5dc505713706a7c75f855e2eaa71b0bf1f6fc60b41765368c89a

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