From mboxrd@z Thu Jan 1 00:00:00 1970 Message-ID: <4E76058F.8050609@domain.hid> Date: Sun, 18 Sep 2011 16:51:59 +0200 From: Gilles Chanteperdrix MIME-Version: 1.0 References: <4E75ED9E.9000708@domain.hid> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Xenomai-core] Port to stmp3xxx (arm based) List-Id: Xenomai life and development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bertold Van den Bergh Cc: xenomai@xenomai.org On 09/18/2011 04:43 PM, Bertold Van den Bergh wrote: > Hello, > > Thanks for the reply. The timer register has the following layout: bit > 0-15: reload, bit 16-31: counter. Thats why I put 0xFFFF0000. Looking > at the code this cannot work so I added an extra field to indicate the > shift after applying the mask. You should really upgrade your I-pipe tree to a more recent one, where the support for tsc emulation was factored. You would add the new case to the tsc implementations in kernel-space, and nowhere else. When you are done, please send a patch. > > Now the userspace latency test prorgam gives valid latencies, sadly > it's still -1ms to 3ms latency. > > How should I proceed troubleshooting this? > Looking at the ipipe trace it looks the task is brought op quite fast > after the interrupt fires so I think it is set at the wrong time, I'm > going to look into this. The I-pipe tracer has a trace point at the point where the timer was supposed to tick. -- Gilles.