Re: [Qemu-devel] [PATCH] isa: Avoid using obsolete memory_region_set_offset for old portio

[Jan Kiszka <jan.kiszka@web.de>]

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On 2011-09-19 14:14, Avi Kivity wrote:
> On 09/18/2011 10:04 PM, Jan Kiszka wrote:
>> >
>> >  If you make the core patch add both mr->offset and mrp->offset, then
>> >  change isa to drop memory_region_set_offset(), instead adding the
>> delta
>> >  to mrp->offset, does that not work out?
>>
>> Nope. The old API accepted arbitrary portio lists per memory region, the
>> new requires one region with a consistent offset per range. I should
>> have documented it...
> 
> What does "a consistent offset per range" mean?  You aren't actually
> changing the caller's ranges.

I'm changing the way isa_register_portio_1 registers portios with the
core: only one per offset. The new commit log says:

"This implies that MemoryRegionPortio::offset is no longer used as
offset within the memory region but just as a correction value for the
offset passed to legacy handlers that expect absolute port addresses."

> 
> 
>>
>> >
>> >>  >    And I
>> >>  >   don't want to remove memory_region_set_offset() until
>> everything (that
>> >>  >   can potentially use it, at least) has been converted.
>> >>
>> >>  IMO it's easier to fix those potential users before converting
>> them. You
>> >>  need to review them anyway to decide if an offset might be needed,
>> and
>> >>  which one precisely.
>> >>
>> >>  Are you aware of any candidates? For PIO, there should be none now.
>> >
>> >  For pio, none, but mmio has some:
>> >
>> >  hw/sh7750.c:    cpu_register_physical_memory_offset(0x1f000000,
>> 0x1000,
>> >  hw/sh7750.c:    cpu_register_physical_memory_offset(0xff000000,
>> 0x1000,
>> >  hw/sh7750.c:    cpu_register_physical_memory_offset(0x1f800000,
>> 0x1000,
>> >  hw/sh7750.c:    cpu_register_physical_memory_offset(0xff800000,
>> 0x1000,
>> >  hw/sh7750.c:    cpu_register_physical_memory_offset(0x1fc00000,
>> 0x1000,
>> >  hw/sh7750.c:    cpu_register_physical_memory_offset(0xffc00000,
>> 0x1000,
>> >  hw/sh_intc.c:
>> >  cpu_register_physical_memory_offset(P4ADDR(address), 4,
>> >  hw/sh_intc.c:
>> >  cpu_register_physical_memory_offset(A7ADDR(address), 4,
>>
>> Cool, that's all. Trivial to fix, just push the offset math into those
>> few handler. Then we can drop cpu_register_physical_memory_offset as
>> well.
> 
> They all use the same handler, so you need to split e.g.
> sh7750_io_memory into six MemoryRegionsOps. Or use tricks with aliases -
> have one giant 4G region with one handler, and map six 4k aliases into
> the system address space.

Looks more like 3 regions with one alias each. But we likely need to
disentangle all that logic first. I would be surprised if there wasn't a
more readable way to express it via the memory API.

Jan


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