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From: Kevin Wolf <kwolf@redhat.com>
To: Daniel Verkamp <daniel@drv.nu>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] ahci: add port I/O index-data pair
Date: Wed, 21 Sep 2011 14:57:21 +0200	[thread overview]
Message-ID: <4E79DF31.9070601@redhat.com> (raw)
In-Reply-To: <4E79D9E1.4060602@redhat.com>

Am 21.09.2011 14:34, schrieb Kevin Wolf:
> Am 27.08.2011 11:12, schrieb Daniel Verkamp:
>> Implement an I/O space index-data register pair as defined by the AHCI
>> spec, including the corresponding SATA PCI capability and BAR.
>>
>> This allows real-mode code to access the AHCI registers; real-mode
>> code cannot address the memory-mapped register space because it is
>> beyond the first megabyte.
>>
>> Signed-off-by: Daniel Verkamp <daniel@drv.nu>
> 
> Thanks, applied to the block branch.
> 
>> --- a/hw/ide/ich.c
>> +++ b/hw/ide/ich.c
>> @@ -72,6 +72,14 @@
>>  #include <hw/ide/pci.h>
>>  #include <hw/ide/ahci.h>
>>  
>> +#define ICH9_SATA_CAP_OFFSET    0xA8
>> +
>> +#define ICH9_IDP_BAR            4
>> +#define ICH9_MEM_BAR            5
>> +
>> +#define ICH9_IDP_INDEX          0x10
>> +#define ICH9_IDP_INDEX_LOG2     0x04
> 
> Just wondering, why did you choose 0x10 and not 0? The spec reads as if
> the implementation could freely choose this, and I can't see what the
> first 16 Bytes are used for.

I forgot that we're not implementing a generic AHCI controller here but
an ICH9 one, which does define the offsets used. Now I'm convinced. :-)

Kevin

      reply	other threads:[~2011-09-21 12:54 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-08-27  9:12 [Qemu-devel] [PATCH] ahci: add port I/O index-data pair Daniel Verkamp
2011-08-28 18:48 ` Alexander Graf
2011-08-30  3:07   ` Daniel Verkamp
2011-09-01 14:58     ` Alexander Graf
2011-09-08  7:33       ` Daniel Verkamp
2011-09-20 13:39   ` Kevin Wolf
2011-09-20 14:02     ` Alexander Graf
2011-09-21 12:34 ` Kevin Wolf
2011-09-21 12:57   ` Kevin Wolf [this message]

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