diff for duplicates of <4E80BEA3.1030803@gmail.com> diff --git a/a/1.txt b/N1/1.txt index 53ffcbc..17fd96d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -8,7 +8,7 @@ On 09/26/2011 10:24 AM, Jamie Iles wrote: > v2: - change timer compatible strings to be more soc specific > - split vic node into 2 devices > -> Signed-off-by: Jamie Iles <jamie@jamieiles.com> +> Signed-off-by: Jamie Iles <jamie-wmLquQDDieKakBO8gow8eQ@public.gmane.org> > --- > arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 249 ++++++++++++++++++++++ > arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 365 ++++++++++++++++++++++++++++++++ @@ -45,7 +45,7 @@ On 09/26/2011 10:24 AM, Jamie Iles wrote: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,1176jz-s"; > + clock-frequency = <400000000>; > + reg = <0>; @@ -65,7 +65,7 @@ re-work the binding. > + #size-cells = <1>; > + ranges; > + -> + pclk: clock at 0 { +> + pclk: clock@0 { > + compatible = "fixed-clock"; > + clock-outputs = "bus", "pclk"; > + clock-frequency = <200000000>; @@ -79,30 +79,30 @@ re-work the binding. > + #size-cells = <1>; > + ranges = <0 0x80000000 0x400000>; > + -> + emac: gem at 30000 { +> + emac: gem@30000 { ethernet is the preferred generic name here. See section 2.2.2 of ePAPR. -So it would be "emac: ethernet at 30000" +So it would be "emac: ethernet@30000" > + compatible = "cadence,gem"; > + reg = <0x30000 0x10000>; > + interrupts = <31>; > + }; > + -> + dmac1: dmac at 40000 { +> + dmac1: dmac@40000 { > + compatible = "snps,dw-dmac"; > + reg = <0x40000 0x10000>; > + interrupts = <25>; > + }; > + -> + dmac2: dmac at 50000 { +> + dmac2: dmac@50000 { > + compatible = "snps,dw-dmac"; > + reg = <0x50000 0x10000>; > + interrupts = <26>; > + }; > + -> + vic0: interrupt-controller at 60000 { +> + vic0: interrupt-controller@60000 { > + compatible = "arm,pl192-vic"; > + interrupt-controller; > + reg = <0x60000 0x1000>; @@ -112,26 +112,26 @@ No edge/level control/settings for the vic? Needs binding documentation. > + }; > + -> + vic1: interrupt-controller at 64000 { +> + vic1: interrupt-controller@64000 { > + compatible = "arm,pl192-vic"; > + interrupt-controller; > + reg = <0x64000 0x1000>; > + #interrupt-cells = <1>; > + }; > + -> + fuse: picoxcell-fuse at 80000 { +> + fuse: picoxcell-fuse@80000 { > + compatible = "picoxcell,fuse-pc3x2"; > + reg = <0x80000 0x10000>; > + }; > + -> + ssi: picoxcell-spi at 90000 { +> + ssi: picoxcell-spi@90000 { > + compatible = "picoxcell,spi"; > + reg = <0x90000 0x10000>; > + interrupt-parent = <&vic0>; > + interrupts = <10>; > + }; > + -> + ipsec: spacc at 100000 { +> + ipsec: spacc@100000 { > + compatible = "picochip,spacc-ipsec"; > + reg = <0x100000 0x10000>; > + interrupt-parent = <&vic0>; @@ -139,14 +139,14 @@ No edge/level control/settings for the vic? Needs binding documentation. > + ref-clock = <&pclk>, "ref"; > + }; > + -> + srtp: spacc at 140000 { +> + srtp: spacc@140000 { > + compatible = "picochip,spacc-srtp"; > + reg = <0x140000 0x10000>; > + interrupt-parent = <&vic0>; > + interrupts = <23>; > + }; > + -> + l2_engine: spacc at 180000 { +> + l2_engine: spacc@180000 { > + compatible = "picochip,spacc-l2"; > + reg = <0x180000 0x10000>; > + interrupt-parent = <&vic0>; @@ -160,7 +160,7 @@ No edge/level control/settings for the vic? Needs binding documentation. > + #size-cells = <1>; > + ranges = <0 0x200000 0x80000>; > + -> + rtc0: rtc at 00000 { +> + rtc0: rtc@00000 { > + compatible = "picochip,pc3x2-rtc"; > + clock-freq = <200000000>; > + reg = <0x00000 0xf>; @@ -168,7 +168,7 @@ No edge/level control/settings for the vic? Needs binding documentation. > + interrupts = <8>; > + }; > + -> + timer0: timer at 10000 { +> + timer0: timer@10000 { > + compatible = "picochip,pc3x2-timer"; > + interrupt-parent = <&vic0>; > + interrupts = <4>; @@ -176,7 +176,7 @@ No edge/level control/settings for the vic? Needs binding documentation. > + reg = <0x10000 0x14>; > + }; > + -> + timer1: timer at 10014 { +> + timer1: timer@10014 { > + compatible = "picochip,pc3x2-timer"; > + interrupt-parent = <&vic0>; > + interrupts = <5>; @@ -184,7 +184,7 @@ No edge/level control/settings for the vic? Needs binding documentation. > + reg = <0x10014 0x14>; > + }; > + -> + timer2: timer at 10028 { +> + timer2: timer@10028 { > + compatible = "picochip,pc3x2-timer"; > + interrupt-parent = <&vic0>; > + interrupts = <6>; @@ -192,7 +192,7 @@ No edge/level control/settings for the vic? Needs binding documentation. > + reg = <0x10028 0x14>; > + }; > + -> + timer3: timer at 1003c { +> + timer3: timer@1003c { > + compatible = "picochip,pc3x2-timer"; > + interrupt-parent = <&vic0>; > + interrupts = <7>; @@ -200,14 +200,14 @@ No edge/level control/settings for the vic? Needs binding documentation. > + reg = <0x1003c 0x14>; > + }; > + -> + gpio: gpio at 20000 { +> + gpio: gpio@20000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0x20000 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + reg-io-width = <4>; > + -> + banka: gpio-controller at 0 { +> + banka: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-bank"; > + gpio-controller; > + #gpio-cells = <2>; @@ -221,7 +221,7 @@ This seems like Linux creeping into device tree. > + regoffset-dirout = <0x04>; > + }; > + -> + bankb: gpio-controller at 1 { +> + bankb: gpio-controller@1 { > + compatible = "snps,dw-apb-gpio-bank"; > + gpio-controller; > + #gpio-cells = <2>; @@ -233,9 +233,9 @@ This seems like Linux creeping into device tree. > + }; > + }; > + -> + uart0: uart at 30000 { +> + uart0: uart@30000 { -Preferred name is serial at 30000 +Preferred name is serial@30000 > + compatible = "snps,dw-apb-uart"; > + reg = <0x30000 0x1000>; @@ -246,7 +246,7 @@ Preferred name is serial at 30000 > + reg-io-width = <4>; > + }; > + -> + uart1: uart at 40000 { +> + uart1: uart@40000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x40000 0x1000>; > + interrupt-parent = <&vic1>; @@ -256,7 +256,7 @@ Preferred name is serial at 30000 > + reg-io-width = <4>; > + }; > + -> + wdog: watchdog at 50000 { +> + wdog: watchdog@50000 { > + compatible = "snps,dw-apb-wdg"; > + reg = <0x50000 0x10000>; > + interrupt-parent = <&vic0>; @@ -272,7 +272,7 @@ Preferred name is serial at 30000 > + compatible = "simple-bus"; > + ranges; > + -> + ebi at 50000000 { +> + ebi@50000000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <1>; @@ -282,7 +282,7 @@ Preferred name is serial at 30000 > + 3 0 0x58000000 0x08000000>; > + }; > + -> + axi2pico at c0000000 { +> + axi2pico@c0000000 { > + compatible = "picochip,axi2pico-pc3x2"; > + reg = <0xc0000000 0x10000>; > + interrupts = <13 14 15 16 17 18 19 20 21>; @@ -323,7 +323,7 @@ Rob > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,1176jz-s"; > + cpu-clock = <&arm_clk>, "cpu"; > + reg = <0>; @@ -339,13 +339,13 @@ Rob > + #size-cells = <1>; > + ranges; > + -> + clkgate: clkgate at 800a0048 { +> + clkgate: clkgate@800a0048 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x800a0048 4>; > + compatible = "picochip,pc3x3-clk-gate"; > + -> + tzprot_clk: clock at 0 { +> + tzprot_clk: clock@0 { > + compatible = "picochip,pc3x3-gated-clk"; > + clock-outputs = "bus"; > + picochip,clk-disable-bit = <0>; @@ -353,7 +353,7 @@ Rob > + ref-clock = <&ref_clk>, "ref"; > + }; > + -> + spi_clk: clock at 1 { +> + spi_clk: clock@1 { > + compatible = "picochip,pc3x3-gated-clk"; > + clock-outputs = "bus"; > + picochip,clk-disable-bit = <1>; @@ -361,7 +361,7 @@ Rob > + ref-clock = <&ref_clk>, "ref"; > + }; > + -> + dmac0_clk: clock at 2 { +> + dmac0_clk: clock@2 { > + compatible = "picochip,pc3x3-gated-clk"; > + clock-outputs = "bus"; > + picochip,clk-disable-bit = <2>; @@ -369,7 +369,7 @@ Rob > + ref-clock = <&ref_clk>, "ref"; > + }; > + -> + dmac1_clk: clock at 3 { +> + dmac1_clk: clock@3 { > + compatible = "picochip,pc3x3-gated-clk"; > + clock-outputs = "bus"; > + picochip,clk-disable-bit = <3>; @@ -377,7 +377,7 @@ Rob > + ref-clock = <&ref_clk>, "ref"; > + }; > + -> + ebi_clk: clock at 4 { +> + ebi_clk: clock@4 { > + compatible = "picochip,pc3x3-gated-clk"; > + clock-outputs = "bus"; > + picochip,clk-disable-bit = <4>; @@ -385,7 +385,7 @@ Rob > + ref-clock = <&ref_clk>, "ref"; > + }; > + -> + ipsec_clk: clock at 5 { +> + ipsec_clk: clock@5 { > + compatible = "picochip,pc3x3-gated-clk"; > + clock-outputs = "bus"; > + picochip,clk-disable-bit = <5>; @@ -393,7 +393,7 @@ Rob > + ref-clock = <&ref_clk>, "ref"; > + }; > + -> + l2_clk: clock at 6 { +> + l2_clk: clock@6 { > + compatible = "picochip,pc3x3-gated-clk"; > + clock-outputs = "bus"; > + picochip,clk-disable-bit = <6>; @@ -401,7 +401,7 @@ Rob > + ref-clock = <&ref_clk>, "ref"; > + }; > + -> + trng_clk: clock at 7 { +> + trng_clk: clock@7 { > + compatible = "picochip,pc3x3-gated-clk"; > + clock-outputs = "bus"; > + picochip,clk-disable-bit = <7>; @@ -409,7 +409,7 @@ Rob > + ref-clock = <&ref_clk>, "ref"; > + }; > + -> + fuse_clk: clock at 8 { +> + fuse_clk: clock@8 { > + compatible = "picochip,pc3x3-gated-clk"; > + clock-outputs = "bus"; > + picochip,clk-disable-bit = <8>; @@ -417,7 +417,7 @@ Rob > + ref-clock = <&ref_clk>, "ref"; > + }; > + -> + otp_clk: clock at 9 { +> + otp_clk: clock@9 { > + compatible = "picochip,pc3x3-gated-clk"; > + clock-outputs = "bus"; > + picochip,clk-disable-bit = <9>; @@ -426,7 +426,7 @@ Rob > + }; > + }; > + -> + arm_clk: clock at 11 { +> + arm_clk: clock@11 { > + compatible = "picochip,pc3x3-pll"; > + reg = <0x800a0050 0x8>; > + picochip,min-freq = <140000000>; @@ -435,7 +435,7 @@ Rob > + clock-outputs = "cpu"; > + }; > + -> + pclk: clock at 12 { +> + pclk: clock@12 { > + compatible = "fixed-clock"; > + clock-outputs = "bus", "pclk"; > + clock-frequency = <200000000>; @@ -449,54 +449,54 @@ Rob > + #size-cells = <1>; > + ranges = <0 0x80000000 0x400000>; > + -> + emac: gem at 30000 { +> + emac: gem@30000 { > + compatible = "cadence,gem"; > + reg = <0x30000 0x10000>; > + interrupt-parent = <&vic0>; > + interrupts = <31>; > + }; > + -> + dmac1: dmac at 40000 { +> + dmac1: dmac@40000 { > + compatible = "snps,dw-dmac"; > + reg = <0x40000 0x10000>; > + interrupt-parent = <&vic0>; > + interrupts = <25>; > + }; > + -> + dmac2: dmac at 50000 { +> + dmac2: dmac@50000 { > + compatible = "snps,dw-dmac"; > + reg = <0x50000 0x10000>; > + interrupt-parent = <&vic0>; > + interrupts = <26>; > + }; > + -> + vic0: interrupt-controller at 60000 { +> + vic0: interrupt-controller@60000 { > + compatible = "arm,pl192-vic"; > + interrupt-controller; > + reg = <0x60000 0x1000>; > + #interrupt-cells = <1>; > + }; > + -> + vic1: interrupt-controller at 64000 { +> + vic1: interrupt-controller@64000 { > + compatible = "arm,pl192-vic"; > + interrupt-controller; > + reg = <0x64000 0x1000>; > + #interrupt-cells = <1>; > + }; > + -> + fuse: picoxcell-fuse at 80000 { +> + fuse: picoxcell-fuse@80000 { > + compatible = "picoxcell,fuse-pc3x3"; > + reg = <0x80000 0x10000>; > + }; > + -> + ssi: picoxcell-spi at 90000 { +> + ssi: picoxcell-spi@90000 { > + compatible = "picoxcell,spi"; > + reg = <0x90000 0x10000>; > + interrupt-parent = <&vic0>; > + interrupts = <10>; > + }; > + -> + ipsec: spacc at 100000 { +> + ipsec: spacc@100000 { > + compatible = "picochip,spacc-ipsec"; > + reg = <0x100000 0x10000>; > + interrupt-parent = <&vic0>; @@ -504,14 +504,14 @@ Rob > + ref-clock = <&ipsec_clk>, "ref"; > + }; > + -> + srtp: spacc at 140000 { +> + srtp: spacc@140000 { > + compatible = "picochip,spacc-srtp"; > + reg = <0x140000 0x10000>; > + interrupt-parent = <&vic0>; > + interrupts = <23>; > + }; > + -> + l2_engine: spacc at 180000 { +> + l2_engine: spacc@180000 { > + compatible = "picochip,spacc-l2"; > + reg = <0x180000 0x10000>; > + interrupt-parent = <&vic0>; @@ -525,7 +525,7 @@ Rob > + #size-cells = <1>; > + ranges = <0 0x200000 0x80000>; > + -> + rtc0: rtc at 00000 { +> + rtc0: rtc@00000 { > + compatible = "picochip,pc3x2-rtc"; > + clock-freq = <200000000>; > + reg = <0x00000 0xf>; @@ -533,7 +533,7 @@ Rob > + interrupts = <8>; > + }; > + -> + timer0: timer at 10000 { +> + timer0: timer@10000 { > + compatible = "picochip,pc3x2-timer"; > + interrupt-parent = <&vic0>; > + interrupts = <4>; @@ -541,7 +541,7 @@ Rob > + reg = <0x10000 0x14>; > + }; > + -> + timer1: timer at 10014 { +> + timer1: timer@10014 { > + compatible = "picochip,pc3x2-timer"; > + interrupt-parent = <&vic0>; > + interrupts = <5>; @@ -549,14 +549,14 @@ Rob > + reg = <0x10014 0x14>; > + }; > + -> + gpio: gpio at 20000 { +> + gpio: gpio@20000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0x20000 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + reg-io-width = <4>; > + -> + banka: gpio-controller at 0 { +> + banka: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-bank"; > + gpio-controller; > + #gpio-cells = <2>; @@ -567,7 +567,7 @@ Rob > + regoffset-dirout = <0x04>; > + }; > + -> + bankb: gpio-controller at 1 { +> + bankb: gpio-controller@1 { > + compatible = "snps,dw-apb-gpio-bank"; > + gpio-controller; > + #gpio-cells = <2>; @@ -578,7 +578,7 @@ Rob > + regoffset-dirout = <0x10>; > + }; > + -> + bankd: gpio-controller at 2 { +> + bankd: gpio-controller@2 { > + compatible = "snps,dw-apb-gpio-bank"; > + gpio-controller; > + #gpio-cells = <2>; @@ -590,7 +590,7 @@ Rob > + }; > + }; > + -> + uart0: uart at 30000 { +> + uart0: uart@30000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x30000 0x1000>; > + interrupt-parent = <&vic1>; @@ -600,7 +600,7 @@ Rob > + reg-io-width = <4>; > + }; > + -> + uart1: uart at 40000 { +> + uart1: uart@40000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x40000 0x1000>; > + interrupt-parent = <&vic1>; @@ -610,7 +610,7 @@ Rob > + reg-io-width = <4>; > + }; > + -> + wdog: watchdog at 50000 { +> + wdog: watchdog@50000 { > + compatible = "snps,dw-apb-wdg"; > + reg = <0x50000 0x10000>; > + interrupt-parent = <&vic0>; @@ -618,7 +618,7 @@ Rob > + bus-clock = <&pclk>, "bus"; > + }; > + -> + timer2: timer at 60000 { +> + timer2: timer@60000 { > + compatible = "picochip,pc3x2-timer"; > + interrupt-parent = <&vic0>; > + interrupts = <6>; @@ -626,7 +626,7 @@ Rob > + reg = <0x60000 0x14>; > + }; > + -> + timer3: timer at 60014 { +> + timer3: timer@60014 { > + compatible = "picochip,pc3x2-timer"; > + interrupt-parent = <&vic0>; > + interrupts = <7>; @@ -642,7 +642,7 @@ Rob > + compatible = "simple-bus"; > + ranges; > + -> + ebi at 50000000 { +> + ebi@50000000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <1>; @@ -652,14 +652,14 @@ Rob > + 3 0 0x58000000 0x08000000>; > + }; > + -> + axi2pico at c0000000 { +> + axi2pico@c0000000 { > + compatible = "picochip,axi2pico-pc3x3"; > + reg = <0xc0000000 0x10000>; > + interrupt-parent = <&vic0>; > + interrupts = <13 14 15 16 17 18 19 20 21>; > + }; > + -> + otp at ffff8000 { +> + otp@ffff8000 { > + compatible = "picochip,otp-pc3x3"; > + reg = <0xffff8000 0x8000>; > + }; diff --git a/a/content_digest b/N1/content_digest index fdb2073..ada902f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,12 @@ "ref\01317050689-16417-1-git-send-email-jamie@jamieiles.com\0" "ref\01317050689-16417-3-git-send-email-jamie@jamieiles.com\0" - "From\0robherring2@gmail.com (Rob Herring)\0" - "Subject\0[PATCHv3 2/4] picoxcell: add the DTS for pc3x2 and pc3x3 devices\0" + "ref\01317050689-16417-3-git-send-email-jamie-wmLquQDDieKakBO8gow8eQ@public.gmane.org\0" + "From\0Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Subject\0Re: [PATCHv3 2/4] picoxcell: add the DTS for pc3x2 and pc3x3 devices\0" "Date\0Mon, 26 Sep 2011 13:04:19 -0500\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Jamie Iles <jamie-wmLquQDDieKakBO8gow8eQ@public.gmane.org>\0" + "Cc\0devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org" + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "Jamie,\n" @@ -16,7 +19,7 @@ "> v2:\t- change timer compatible strings to be more soc specific\n" "> \t- split vic node into 2 devices\n" "> \n" - "> Signed-off-by: Jamie Iles <jamie@jamieiles.com>\n" + "> Signed-off-by: Jamie Iles <jamie-wmLquQDDieKakBO8gow8eQ@public.gmane.org>\n" "> ---\n" "> arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 249 ++++++++++++++++++++++\n" "> arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 365 ++++++++++++++++++++++++++++++++\n" @@ -53,7 +56,7 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,1176jz-s\";\n" "> +\t\t\tclock-frequency = <400000000>;\n" "> +\t\t\treg = <0>;\n" @@ -73,7 +76,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tpclk: clock at 0 {\n" + "> +\t\tpclk: clock@0 {\n" "> +\t\t\tcompatible = \"fixed-clock\";\n" "> +\t\t\tclock-outputs = \"bus\", \"pclk\";\n" "> +\t\t\tclock-frequency = <200000000>;\n" @@ -87,30 +90,30 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges = <0 0x80000000 0x400000>;\n" "> +\n" - "> +\t\temac: gem at 30000 {\n" + "> +\t\temac: gem@30000 {\n" "\n" "ethernet is the preferred generic name here. See section 2.2.2 of ePAPR.\n" "\n" - "So it would be \"emac: ethernet at 30000\"\n" + "So it would be \"emac: ethernet@30000\"\n" "\n" "> +\t\t\tcompatible = \"cadence,gem\";\n" "> +\t\t\treg = <0x30000 0x10000>;\n" "> +\t\t\tinterrupts = <31>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdmac1: dmac at 40000 {\n" + "> +\t\tdmac1: dmac@40000 {\n" "> +\t\t\tcompatible = \"snps,dw-dmac\";\n" "> +\t\t\treg = <0x40000 0x10000>;\n" "> +\t\t\tinterrupts = <25>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdmac2: dmac at 50000 {\n" + "> +\t\tdmac2: dmac@50000 {\n" "> +\t\t\tcompatible = \"snps,dw-dmac\";\n" "> +\t\t\treg = <0x50000 0x10000>;\n" "> +\t\t\tinterrupts = <26>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tvic0: interrupt-controller at 60000 {\n" + "> +\t\tvic0: interrupt-controller@60000 {\n" "> +\t\t\tcompatible = \"arm,pl192-vic\";\n" "> +\t\t\tinterrupt-controller;\n" "> +\t\t\treg = <0x60000 0x1000>;\n" @@ -120,26 +123,26 @@ "\n" "> +\t\t};\n" "> +\n" - "> +\t\tvic1: interrupt-controller at 64000 {\n" + "> +\t\tvic1: interrupt-controller@64000 {\n" "> +\t\t\tcompatible = \"arm,pl192-vic\";\n" "> +\t\t\tinterrupt-controller;\n" "> +\t\t\treg = <0x64000 0x1000>;\n" "> +\t\t\t#interrupt-cells = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tfuse: picoxcell-fuse at 80000 {\n" + "> +\t\tfuse: picoxcell-fuse@80000 {\n" "> +\t\t\tcompatible = \"picoxcell,fuse-pc3x2\";\n" "> +\t\t\treg = <0x80000 0x10000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tssi: picoxcell-spi at 90000 {\n" + "> +\t\tssi: picoxcell-spi@90000 {\n" "> +\t\t\tcompatible = \"picoxcell,spi\";\n" "> +\t\t\treg = <0x90000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\tinterrupts = <10>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tipsec: spacc at 100000 {\n" + "> +\t\tipsec: spacc@100000 {\n" "> +\t\t\tcompatible = \"picochip,spacc-ipsec\";\n" "> +\t\t\treg = <0x100000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&vic0>;\n" @@ -147,14 +150,14 @@ "> +\t\t\tref-clock = <&pclk>, \"ref\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tsrtp: spacc at 140000 {\n" + "> +\t\tsrtp: spacc@140000 {\n" "> +\t\t\tcompatible = \"picochip,spacc-srtp\";\n" "> +\t\t\treg = <0x140000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\tinterrupts = <23>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tl2_engine: spacc at 180000 {\n" + "> +\t\tl2_engine: spacc@180000 {\n" "> +\t\t\tcompatible = \"picochip,spacc-l2\";\n" "> +\t\t\treg = <0x180000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&vic0>;\n" @@ -168,7 +171,7 @@ "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0 0x200000 0x80000>;\n" "> +\n" - "> +\t\t\trtc0: rtc at 00000 {\n" + "> +\t\t\trtc0: rtc@00000 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x2-rtc\";\n" "> +\t\t\t\tclock-freq = <200000000>;\n" "> +\t\t\t\treg = <0x00000 0xf>;\n" @@ -176,7 +179,7 @@ "> +\t\t\t\tinterrupts = <8>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer0: timer at 10000 {\n" + "> +\t\t\ttimer0: timer@10000 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x2-timer\";\n" "> +\t\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\t\tinterrupts = <4>;\n" @@ -184,7 +187,7 @@ "> +\t\t\t\treg = <0x10000 0x14>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer1: timer at 10014 {\n" + "> +\t\t\ttimer1: timer@10014 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x2-timer\";\n" "> +\t\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\t\tinterrupts = <5>;\n" @@ -192,7 +195,7 @@ "> +\t\t\t\treg = <0x10014 0x14>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer2: timer at 10028 {\n" + "> +\t\t\ttimer2: timer@10028 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x2-timer\";\n" "> +\t\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\t\tinterrupts = <6>;\n" @@ -200,7 +203,7 @@ "> +\t\t\t\treg = <0x10028 0x14>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer3: timer at 1003c {\n" + "> +\t\t\ttimer3: timer@1003c {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x2-timer\";\n" "> +\t\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\t\tinterrupts = <7>;\n" @@ -208,14 +211,14 @@ "> +\t\t\t\treg = <0x1003c 0x14>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tgpio: gpio at 20000 {\n" + "> +\t\t\tgpio: gpio@20000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-gpio\";\n" "> +\t\t\t\treg = <0x20000 0x1000>;\n" "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\t\t\t\treg-io-width = <4>;\n" "> +\n" - "> +\t\t\t\tbanka: gpio-controller at 0 {\n" + "> +\t\t\t\tbanka: gpio-controller@0 {\n" "> +\t\t\t\t\tcompatible = \"snps,dw-apb-gpio-bank\";\n" "> +\t\t\t\t\tgpio-controller;\n" "> +\t\t\t\t\t#gpio-cells = <2>;\n" @@ -229,7 +232,7 @@ "> +\t\t\t\t\tregoffset-dirout = <0x04>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tbankb: gpio-controller at 1 {\n" + "> +\t\t\t\tbankb: gpio-controller@1 {\n" "> +\t\t\t\t\tcompatible = \"snps,dw-apb-gpio-bank\";\n" "> +\t\t\t\t\tgpio-controller;\n" "> +\t\t\t\t\t#gpio-cells = <2>;\n" @@ -241,9 +244,9 @@ "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0: uart at 30000 {\n" + "> +\t\t\tuart0: uart@30000 {\n" "\n" - "Preferred name is serial at 30000\n" + "Preferred name is serial@30000\n" "\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\t\treg = <0x30000 0x1000>;\n" @@ -254,7 +257,7 @@ "> +\t\t\t\treg-io-width = <4>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart1: uart at 40000 {\n" + "> +\t\t\tuart1: uart@40000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\t\treg = <0x40000 0x1000>;\n" "> +\t\t\t\tinterrupt-parent = <&vic1>;\n" @@ -264,7 +267,7 @@ "> +\t\t\t\treg-io-width = <4>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\twdog: watchdog at 50000 {\n" + "> +\t\t\twdog: watchdog@50000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-wdg\";\n" "> +\t\t\t\treg = <0x50000 0x10000>;\n" "> +\t\t\t\tinterrupt-parent = <&vic0>;\n" @@ -280,7 +283,7 @@ "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tebi at 50000000 {\n" + "> +\t\tebi@50000000 {\n" "> +\t\t\tcompatible = \"simple-bus\";\n" "> +\t\t\t#address-cells = <2>;\n" "> +\t\t\t#size-cells = <1>;\n" @@ -290,7 +293,7 @@ "> +\t\t\t\t 3 0 0x58000000 0x08000000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\taxi2pico at c0000000 {\n" + "> +\t\taxi2pico@c0000000 {\n" "> +\t\t\tcompatible = \"picochip,axi2pico-pc3x2\";\n" "> +\t\t\treg = <0xc0000000 0x10000>;\n" "> +\t\t\tinterrupts = <13 14 15 16 17 18 19 20 21>;\n" @@ -331,7 +334,7 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,1176jz-s\";\n" "> +\t\t\tcpu-clock = <&arm_clk>, \"cpu\";\n" "> +\t\t\treg = <0>;\n" @@ -347,13 +350,13 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tclkgate: clkgate at 800a0048 {\n" + "> +\t\tclkgate: clkgate@800a0048 {\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <0>;\n" "> +\t\t\treg = <0x800a0048 4>;\n" "> +\t\t\tcompatible = \"picochip,pc3x3-clk-gate\";\n" "> +\n" - "> +\t\t\ttzprot_clk: clock at 0 {\n" + "> +\t\t\ttzprot_clk: clock@0 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x3-gated-clk\";\n" "> +\t\t\t\tclock-outputs = \"bus\";\n" "> +\t\t\t\tpicochip,clk-disable-bit = <0>;\n" @@ -361,7 +364,7 @@ "> +\t\t\t\tref-clock = <&ref_clk>, \"ref\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tspi_clk: clock at 1 {\n" + "> +\t\t\tspi_clk: clock@1 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x3-gated-clk\";\n" "> +\t\t\t\tclock-outputs = \"bus\";\n" "> +\t\t\t\tpicochip,clk-disable-bit = <1>;\n" @@ -369,7 +372,7 @@ "> +\t\t\t\tref-clock = <&ref_clk>, \"ref\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tdmac0_clk: clock at 2 {\n" + "> +\t\t\tdmac0_clk: clock@2 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x3-gated-clk\";\n" "> +\t\t\t\tclock-outputs = \"bus\";\n" "> +\t\t\t\tpicochip,clk-disable-bit = <2>;\n" @@ -377,7 +380,7 @@ "> +\t\t\t\tref-clock = <&ref_clk>, \"ref\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tdmac1_clk: clock at 3 {\n" + "> +\t\t\tdmac1_clk: clock@3 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x3-gated-clk\";\n" "> +\t\t\t\tclock-outputs = \"bus\";\n" "> +\t\t\t\tpicochip,clk-disable-bit = <3>;\n" @@ -385,7 +388,7 @@ "> +\t\t\t\tref-clock = <&ref_clk>, \"ref\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tebi_clk: clock at 4 {\n" + "> +\t\t\tebi_clk: clock@4 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x3-gated-clk\";\n" "> +\t\t\t\tclock-outputs = \"bus\";\n" "> +\t\t\t\tpicochip,clk-disable-bit = <4>;\n" @@ -393,7 +396,7 @@ "> +\t\t\t\tref-clock = <&ref_clk>, \"ref\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tipsec_clk: clock at 5 {\n" + "> +\t\t\tipsec_clk: clock@5 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x3-gated-clk\";\n" "> +\t\t\t\tclock-outputs = \"bus\";\n" "> +\t\t\t\tpicochip,clk-disable-bit = <5>;\n" @@ -401,7 +404,7 @@ "> +\t\t\t\tref-clock = <&ref_clk>, \"ref\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tl2_clk: clock at 6 {\n" + "> +\t\t\tl2_clk: clock@6 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x3-gated-clk\";\n" "> +\t\t\t\tclock-outputs = \"bus\";\n" "> +\t\t\t\tpicochip,clk-disable-bit = <6>;\n" @@ -409,7 +412,7 @@ "> +\t\t\t\tref-clock = <&ref_clk>, \"ref\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttrng_clk: clock at 7 {\n" + "> +\t\t\ttrng_clk: clock@7 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x3-gated-clk\";\n" "> +\t\t\t\tclock-outputs = \"bus\";\n" "> +\t\t\t\tpicochip,clk-disable-bit = <7>;\n" @@ -417,7 +420,7 @@ "> +\t\t\t\tref-clock = <&ref_clk>, \"ref\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tfuse_clk: clock at 8 {\n" + "> +\t\t\tfuse_clk: clock@8 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x3-gated-clk\";\n" "> +\t\t\t\tclock-outputs = \"bus\";\n" "> +\t\t\t\tpicochip,clk-disable-bit = <8>;\n" @@ -425,7 +428,7 @@ "> +\t\t\t\tref-clock = <&ref_clk>, \"ref\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\totp_clk: clock at 9 {\n" + "> +\t\t\totp_clk: clock@9 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x3-gated-clk\";\n" "> +\t\t\t\tclock-outputs = \"bus\";\n" "> +\t\t\t\tpicochip,clk-disable-bit = <9>;\n" @@ -434,7 +437,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tarm_clk: clock at 11 {\n" + "> +\t\tarm_clk: clock@11 {\n" "> +\t\t\tcompatible = \"picochip,pc3x3-pll\";\n" "> +\t\t\treg = <0x800a0050 0x8>;\n" "> +\t\t\tpicochip,min-freq = <140000000>;\n" @@ -443,7 +446,7 @@ "> +\t\t\tclock-outputs = \"cpu\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpclk: clock at 12 {\n" + "> +\t\tpclk: clock@12 {\n" "> +\t\t\tcompatible = \"fixed-clock\";\n" "> +\t\t\tclock-outputs = \"bus\", \"pclk\";\n" "> +\t\t\tclock-frequency = <200000000>;\n" @@ -457,54 +460,54 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges = <0 0x80000000 0x400000>;\n" "> +\n" - "> +\t\temac: gem at 30000 {\n" + "> +\t\temac: gem@30000 {\n" "> +\t\t\tcompatible = \"cadence,gem\";\n" "> +\t\t\treg = <0x30000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\tinterrupts = <31>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdmac1: dmac at 40000 {\n" + "> +\t\tdmac1: dmac@40000 {\n" "> +\t\t\tcompatible = \"snps,dw-dmac\";\n" "> +\t\t\treg = <0x40000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\tinterrupts = <25>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tdmac2: dmac at 50000 {\n" + "> +\t\tdmac2: dmac@50000 {\n" "> +\t\t\tcompatible = \"snps,dw-dmac\";\n" "> +\t\t\treg = <0x50000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\tinterrupts = <26>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tvic0: interrupt-controller at 60000 {\n" + "> +\t\tvic0: interrupt-controller@60000 {\n" "> +\t\t\tcompatible = \"arm,pl192-vic\";\n" "> +\t\t\tinterrupt-controller;\n" "> +\t\t\treg = <0x60000 0x1000>;\n" "> +\t\t\t#interrupt-cells = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tvic1: interrupt-controller at 64000 {\n" + "> +\t\tvic1: interrupt-controller@64000 {\n" "> +\t\t\tcompatible = \"arm,pl192-vic\";\n" "> +\t\t\tinterrupt-controller;\n" "> +\t\t\treg = <0x64000 0x1000>;\n" "> +\t\t\t#interrupt-cells = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tfuse: picoxcell-fuse at 80000 {\n" + "> +\t\tfuse: picoxcell-fuse@80000 {\n" "> +\t\t\tcompatible = \"picoxcell,fuse-pc3x3\";\n" "> +\t\t\treg = <0x80000 0x10000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tssi: picoxcell-spi at 90000 {\n" + "> +\t\tssi: picoxcell-spi@90000 {\n" "> +\t\t\tcompatible = \"picoxcell,spi\";\n" "> +\t\t\treg = <0x90000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\tinterrupts = <10>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tipsec: spacc at 100000 {\n" + "> +\t\tipsec: spacc@100000 {\n" "> +\t\t\tcompatible = \"picochip,spacc-ipsec\";\n" "> +\t\t\treg = <0x100000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&vic0>;\n" @@ -512,14 +515,14 @@ "> +\t\t\tref-clock = <&ipsec_clk>, \"ref\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tsrtp: spacc at 140000 {\n" + "> +\t\tsrtp: spacc@140000 {\n" "> +\t\t\tcompatible = \"picochip,spacc-srtp\";\n" "> +\t\t\treg = <0x140000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\tinterrupts = <23>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tl2_engine: spacc at 180000 {\n" + "> +\t\tl2_engine: spacc@180000 {\n" "> +\t\t\tcompatible = \"picochip,spacc-l2\";\n" "> +\t\t\treg = <0x180000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&vic0>;\n" @@ -533,7 +536,7 @@ "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0 0x200000 0x80000>;\n" "> +\n" - "> +\t\t\trtc0: rtc at 00000 {\n" + "> +\t\t\trtc0: rtc@00000 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x2-rtc\";\n" "> +\t\t\t\tclock-freq = <200000000>;\n" "> +\t\t\t\treg = <0x00000 0xf>;\n" @@ -541,7 +544,7 @@ "> +\t\t\t\tinterrupts = <8>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer0: timer at 10000 {\n" + "> +\t\t\ttimer0: timer@10000 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x2-timer\";\n" "> +\t\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\t\tinterrupts = <4>;\n" @@ -549,7 +552,7 @@ "> +\t\t\t\treg = <0x10000 0x14>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer1: timer at 10014 {\n" + "> +\t\t\ttimer1: timer@10014 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x2-timer\";\n" "> +\t\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\t\tinterrupts = <5>;\n" @@ -557,14 +560,14 @@ "> +\t\t\t\treg = <0x10014 0x14>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tgpio: gpio at 20000 {\n" + "> +\t\t\tgpio: gpio@20000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-gpio\";\n" "> +\t\t\t\treg = <0x20000 0x1000>;\n" "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\t\t\t\treg-io-width = <4>;\n" "> +\n" - "> +\t\t\t\tbanka: gpio-controller at 0 {\n" + "> +\t\t\t\tbanka: gpio-controller@0 {\n" "> +\t\t\t\t\tcompatible = \"snps,dw-apb-gpio-bank\";\n" "> +\t\t\t\t\tgpio-controller;\n" "> +\t\t\t\t\t#gpio-cells = <2>;\n" @@ -575,7 +578,7 @@ "> +\t\t\t\t\tregoffset-dirout = <0x04>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tbankb: gpio-controller at 1 {\n" + "> +\t\t\t\tbankb: gpio-controller@1 {\n" "> +\t\t\t\t\tcompatible = \"snps,dw-apb-gpio-bank\";\n" "> +\t\t\t\t\tgpio-controller;\n" "> +\t\t\t\t\t#gpio-cells = <2>;\n" @@ -586,7 +589,7 @@ "> +\t\t\t\t\tregoffset-dirout = <0x10>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tbankd: gpio-controller at 2 {\n" + "> +\t\t\t\tbankd: gpio-controller@2 {\n" "> +\t\t\t\t\tcompatible = \"snps,dw-apb-gpio-bank\";\n" "> +\t\t\t\t\tgpio-controller;\n" "> +\t\t\t\t\t#gpio-cells = <2>;\n" @@ -598,7 +601,7 @@ "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0: uart at 30000 {\n" + "> +\t\t\tuart0: uart@30000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\t\treg = <0x30000 0x1000>;\n" "> +\t\t\t\tinterrupt-parent = <&vic1>;\n" @@ -608,7 +611,7 @@ "> +\t\t\t\treg-io-width = <4>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart1: uart at 40000 {\n" + "> +\t\t\tuart1: uart@40000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\t\treg = <0x40000 0x1000>;\n" "> +\t\t\t\tinterrupt-parent = <&vic1>;\n" @@ -618,7 +621,7 @@ "> +\t\t\t\treg-io-width = <4>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\twdog: watchdog at 50000 {\n" + "> +\t\t\twdog: watchdog@50000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-wdg\";\n" "> +\t\t\t\treg = <0x50000 0x10000>;\n" "> +\t\t\t\tinterrupt-parent = <&vic0>;\n" @@ -626,7 +629,7 @@ "> +\t\t\t\tbus-clock = <&pclk>, \"bus\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer2: timer at 60000 {\n" + "> +\t\t\ttimer2: timer@60000 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x2-timer\";\n" "> +\t\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\t\tinterrupts = <6>;\n" @@ -634,7 +637,7 @@ "> +\t\t\t\treg = <0x60000 0x14>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer3: timer at 60014 {\n" + "> +\t\t\ttimer3: timer@60014 {\n" "> +\t\t\t\tcompatible = \"picochip,pc3x2-timer\";\n" "> +\t\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\t\tinterrupts = <7>;\n" @@ -650,7 +653,7 @@ "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tebi at 50000000 {\n" + "> +\t\tebi@50000000 {\n" "> +\t\t\tcompatible = \"simple-bus\";\n" "> +\t\t\t#address-cells = <2>;\n" "> +\t\t\t#size-cells = <1>;\n" @@ -660,18 +663,18 @@ "> +\t\t\t\t 3 0 0x58000000 0x08000000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\taxi2pico at c0000000 {\n" + "> +\t\taxi2pico@c0000000 {\n" "> +\t\t\tcompatible = \"picochip,axi2pico-pc3x3\";\n" "> +\t\t\treg = <0xc0000000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&vic0>;\n" "> +\t\t\tinterrupts = <13 14 15 16 17 18 19 20 21>;\n" "> +\t\t};\n" "> +\n" - "> +\t\totp at ffff8000 {\n" + "> +\t\totp@ffff8000 {\n" "> +\t\t\tcompatible = \"picochip,otp-pc3x3\";\n" "> +\t\t\treg = <0xffff8000 0x8000>;\n" "> +\t\t};\n" "> +\t};\n" > +}; -085d41c1a5e6d48e6c948649446f12a7f37e43afafde57ff76713906d9bf35f6 +9f217fd523774cf4cba9635f6eb09349911b59bca02394be67cbabae3bd25bf7
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