From: Sergei Shtylyov <sshtylyov@mvista.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg
Date: Wed, 28 Sep 2011 12:58:45 +0400 [thread overview]
Message-ID: <4E82E1C5.6010501@mvista.com> (raw)
In-Reply-To: <E1R8VUh-0000hD-CK@rhodium.platinum.guralp.com>
Hello.
On 26-09-2011 20:02, Laurence Withers wrote:
> In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
> on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
> This allows 1-bit hardware ECC to work with chip select other than CS2.
> Note this now matches the usage in nand_davinci_enable_hwecc(), which
> already had the correct handling, and allows refactoring to a single
> function encapsulating the register read.
> Without this fix, writing NAND pages to a chip not wired to CS2 would
> result in in the ECC calculation always returning FFFFFF for each
> 512-byte segment, and reading back a correctly written page (one with
> ECC intact) would always fail. With this fix, the ECC is written and
> verified correctly.
You need to sign off your patch. Add this line to the changelog:
Signed-off-by: Laurence Withers <lwithers@guralp.com>
WBR, Sergei
next prev parent reply other threads:[~2011-09-28 8:58 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-26 16:02 [U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg Laurence Withers
2011-09-26 16:02 ` [U-Boot] [PATCH v2] " Laurence Withers
2011-10-10 13:45 ` Laurence Withers
2011-10-10 20:29 ` Scott Wood
2011-09-26 16:02 ` [U-Boot] [PATCH] " Laurence Withers
2011-09-28 8:58 ` Sergei Shtylyov [this message]
2011-09-29 10:18 ` Laurence Withers
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