From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 4/5] softfloat: Implement fused multiply-add
Date: Fri, 30 Sep 2011 08:28:03 -0700 [thread overview]
Message-ID: <4E85E003.1030901@twiddle.net> (raw)
In-Reply-To: <1317230853-24970-5-git-send-email-peter.maydell@linaro.org>
On 09/28/2011 10:27 AM, Peter Maydell wrote:
> /*----------------------------------------------------------------------------
> +| Select which NaN to propagate for a three-input operation.
> +| For the moment we assume that no CPU needs the 'larger significand'
> +| information.
> +| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
> +*----------------------------------------------------------------------------*/
> +#if defined(TARGET_ARM)
> +static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
> + flag cIsQNaN, flag cIsSNaN, flag infzero STATUS_PARAM)
...
> +#elif defined(TARGET_PPC)
> +static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
> + flag cIsQNaN, flag cIsSNaN, flag infzero STATUS_PARAM)
> +{
The function declaration should be outside the #if, so that the interface is
forcibly consistent across the platforms.
> + cSig64 = (uint64_t)cSig << 39;
This might be more readable as << (62 - 23), since you've just mentioned the
explicit bit at bit 62 above.
> + if (pSign == cSign) {
> + /* Addition */
...
> + shift64RightJamming(zSig64, 32, &zSig64);
> + return roundAndPackFloat32(zSign, zExp, zSig64 STATUS_VAR);
> + } else {
> + /* Subtraction */
...
> + shift64RightJamming(zSig64, 32, &zSig64);
> + return roundAndPackFloat32(zSign, zExp, zSig64 STATUS_VAR);
> + }
> +}
Push those two calls down after the IF?
Similar comments wrt float64_muladd. But I don't see any actual logic errors
wrt the handling of any of the edge cases.
r~
next prev parent reply other threads:[~2011-09-30 15:28 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-28 17:27 [Qemu-devel] [PATCH 0/5] target-arm: Implement UDIV/SDIV and fused multiply-accumulate Peter Maydell
2011-09-28 17:27 ` [Qemu-devel] [PATCH 1/5] softfloat: Reinstate accidentally disabled target-specific NaN handling Peter Maydell
2011-09-30 15:03 ` Richard Henderson
2011-09-28 17:27 ` [Qemu-devel] [PATCH 2/5] target-arm: v6 media multiply space: UNDEF on unassigned encodings Peter Maydell
2011-09-28 17:27 ` [Qemu-devel] [PATCH 3/5] target-arm: Add ARM UDIV/SDIV support Peter Maydell
2011-09-28 17:27 ` [Qemu-devel] [PATCH 4/5] softfloat: Implement fused multiply-add Peter Maydell
2011-09-30 15:28 ` Richard Henderson [this message]
2011-09-30 16:12 ` Peter Maydell
2011-09-28 17:27 ` [Qemu-devel] [PATCH 5/5] target-arm: Implement VFPv4 fused multiply-accumulate insns Peter Maydell
2011-09-28 19:13 ` [Qemu-devel] [PATCH 0/5] target-arm: Implement UDIV/SDIV and fused multiply-accumulate Blue Swirl
2011-09-28 19:32 ` Peter Maydell
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