From: Avi Kivity <avi@redhat.com>
To: Jan Kiszka <jan.kiszka@web.de>
Cc: Marcelo Tosatti <mtosatti@redhat.com>,
kvm@vger.kernel.org, qemu-devel@nongnu.org
Subject: Re: [PATCH] i386: wire up MSR_IA32_MISC_ENABLE
Date: Tue, 04 Oct 2011 19:51:43 +0200 [thread overview]
Message-ID: <4E8B47AF.7040903@redhat.com> (raw)
In-Reply-To: <4E8B416A.2090401@web.de>
On 10/04/2011 07:24 PM, Jan Kiszka wrote:
> >>
> >> Given that, when in conflict, we rather model after AMD than Intel for
> >> TCG, I would hesitate to expose this by default. Or are there
> >> precedences already?
> >
> > Practically all MSRs. i486 doesn't have any, IIRC, for example.
>
> Pre-Pentiums don't have instructions to access them as well, so that
> doesn't cause any harm.
kvm doesn't detect this; does tcg? In any case, MSR availability varies
widely with processor model.
> >
> > (and given this MSR has no effect, the only difference it makes to
> > guests is the #GP we take or not; still it may be worthwhile to
> > construct some table-driven thing to allow or reject MSR accesses, both
> > for kvm and qemu)
>
> Right. If this MSR is not the first bogus one on AMD, we can do this
> later. If it is, it should be done first.
It's certainly not the first - they practically all are, depending on
exact model.
--
error compiling committee.c: too many arguments to function
WARNING: multiple messages have this Message-ID (diff)
From: Avi Kivity <avi@redhat.com>
To: Jan Kiszka <jan.kiszka@web.de>
Cc: Marcelo Tosatti <mtosatti@redhat.com>,
qemu-devel@nongnu.org, kvm@vger.kernel.org
Subject: Re: [Qemu-devel] [PATCH] i386: wire up MSR_IA32_MISC_ENABLE
Date: Tue, 04 Oct 2011 19:51:43 +0200 [thread overview]
Message-ID: <4E8B47AF.7040903@redhat.com> (raw)
In-Reply-To: <4E8B416A.2090401@web.de>
On 10/04/2011 07:24 PM, Jan Kiszka wrote:
> >>
> >> Given that, when in conflict, we rather model after AMD than Intel for
> >> TCG, I would hesitate to expose this by default. Or are there
> >> precedences already?
> >
> > Practically all MSRs. i486 doesn't have any, IIRC, for example.
>
> Pre-Pentiums don't have instructions to access them as well, so that
> doesn't cause any harm.
kvm doesn't detect this; does tcg? In any case, MSR availability varies
widely with processor model.
> >
> > (and given this MSR has no effect, the only difference it makes to
> > guests is the #GP we take or not; still it may be worthwhile to
> > construct some table-driven thing to allow or reject MSR accesses, both
> > for kvm and qemu)
>
> Right. If this MSR is not the first bogus one on AMD, we can do this
> later. If it is, it should be done first.
It's certainly not the first - they practically all are, depending on
exact model.
--
error compiling committee.c: too many arguments to function
next prev parent reply other threads:[~2011-10-04 17:51 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-04 14:26 [PATCH] i386: wire up MSR_IA32_MISC_ENABLE Avi Kivity
2011-10-04 14:26 ` [Qemu-devel] " Avi Kivity
2011-10-04 16:05 ` Jan Kiszka
2011-10-04 16:05 ` [Qemu-devel] " Jan Kiszka
2011-10-04 17:08 ` Avi Kivity
2011-10-04 17:08 ` [Qemu-devel] " Avi Kivity
2011-10-04 17:14 ` Jan Kiszka
2011-10-04 17:14 ` [Qemu-devel] " Jan Kiszka
2011-10-04 17:21 ` Avi Kivity
2011-10-04 17:21 ` [Qemu-devel] " Avi Kivity
2011-10-04 17:24 ` Jan Kiszka
2011-10-04 17:24 ` [Qemu-devel] " Jan Kiszka
2011-10-04 17:51 ` Avi Kivity [this message]
2011-10-04 17:51 ` Avi Kivity
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