From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: Re: [PATCH] i386: wire up MSR_IA32_MISC_ENABLE Date: Tue, 04 Oct 2011 19:51:43 +0200 Message-ID: <4E8B47AF.7040903@redhat.com> References: <1317738395-6488-1-git-send-email-avi@redhat.com> <4E8B2EB8.80408@web.de> <4E8B3D83.8050903@redhat.com> <4E8B3EDE.3060306@web.de> <4E8B4087.4060906@redhat.com> <4E8B416A.2090401@web.de> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Cc: Marcelo Tosatti , kvm@vger.kernel.org, qemu-devel@nongnu.org To: Jan Kiszka Return-path: Received: from mx1.redhat.com ([209.132.183.28]:2057 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932845Ab1JDRvr (ORCPT ); Tue, 4 Oct 2011 13:51:47 -0400 In-Reply-To: <4E8B416A.2090401@web.de> Sender: kvm-owner@vger.kernel.org List-ID: On 10/04/2011 07:24 PM, Jan Kiszka wrote: > >> > >> Given that, when in conflict, we rather model after AMD than Intel for > >> TCG, I would hesitate to expose this by default. Or are there > >> precedences already? > > > > Practically all MSRs. i486 doesn't have any, IIRC, for example. > > Pre-Pentiums don't have instructions to access them as well, so that > doesn't cause any harm. kvm doesn't detect this; does tcg? In any case, MSR availability varies widely with processor model. > > > > (and given this MSR has no effect, the only difference it makes to > > guests is the #GP we take or not; still it may be worthwhile to > > construct some table-driven thing to allow or reject MSR accesses, both > > for kvm and qemu) > > Right. If this MSR is not the first bogus one on AMD, we can do this > later. If it is, it should be done first. It's certainly not the first - they practically all are, depending on exact model. -- error compiling committee.c: too many arguments to function From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:48720) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RB99g-0002RL-G8 for qemu-devel@nongnu.org; Tue, 04 Oct 2011 13:51:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RB99f-0001fN-Em for qemu-devel@nongnu.org; Tue, 04 Oct 2011 13:51:48 -0400 Received: from mx1.redhat.com ([209.132.183.28]:10833) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RB99f-0001fI-7V for qemu-devel@nongnu.org; Tue, 04 Oct 2011 13:51:47 -0400 Message-ID: <4E8B47AF.7040903@redhat.com> Date: Tue, 04 Oct 2011 19:51:43 +0200 From: Avi Kivity MIME-Version: 1.0 References: <1317738395-6488-1-git-send-email-avi@redhat.com> <4E8B2EB8.80408@web.de> <4E8B3D83.8050903@redhat.com> <4E8B3EDE.3060306@web.de> <4E8B4087.4060906@redhat.com> <4E8B416A.2090401@web.de> In-Reply-To: <4E8B416A.2090401@web.de> Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] i386: wire up MSR_IA32_MISC_ENABLE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jan Kiszka Cc: Marcelo Tosatti , qemu-devel@nongnu.org, kvm@vger.kernel.org On 10/04/2011 07:24 PM, Jan Kiszka wrote: > >> > >> Given that, when in conflict, we rather model after AMD than Intel for > >> TCG, I would hesitate to expose this by default. Or are there > >> precedences already? > > > > Practically all MSRs. i486 doesn't have any, IIRC, for example. > > Pre-Pentiums don't have instructions to access them as well, so that > doesn't cause any harm. kvm doesn't detect this; does tcg? In any case, MSR availability varies widely with processor model. > > > > (and given this MSR has no effect, the only difference it makes to > > guests is the #GP we take or not; still it may be worthwhile to > > construct some table-driven thing to allow or reject MSR accesses, both > > for kvm and qemu) > > Right. If this MSR is not the first bogus one on AMD, we can do this > later. If it is, it should be done first. It's certainly not the first - they practically all are, depending on exact model. -- error compiling committee.c: too many arguments to function