From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:60279) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RBp8n-0007S3-KA for qemu-devel@nongnu.org; Thu, 06 Oct 2011 10:41:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RBp8i-00021E-Tx for qemu-devel@nongnu.org; Thu, 06 Oct 2011 10:41:41 -0400 Message-ID: <4E8DBE15.7070200@adacore.com> Date: Thu, 06 Oct 2011 16:41:25 +0200 From: Fabien Chouteau MIME-Version: 1.0 References: <1317225245-24360-1-git-send-email-chouteau@adacore.com> In-Reply-To: <1317225245-24360-1-git-send-email-chouteau@adacore.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] Set an invalid-bits mask for each SPE instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, agraf@suse.de On 28/09/2011 17:54, Fabien Chouteau wrote: > SPE instructions are defined by pairs. Currently, the invalid-bits mask is set > for the first instruction, but the second one can have a different mask. > > example: > GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), > Any comments? -- Fabien Chouteau