diff for duplicates of <4E8ECA1B.5010005@arm.com> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index 776eca6..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,5 +0,0 @@ -Content-Type: text/x-patch; - name=0001-ARM-gic-allow-GIC-to-support-non-banked-setups.patch -Content-Transfer-Encoding: quoted-printable -Content-Disposition: inline; - filename*0="0001-ARM-gic-allow-GIC-to-support-non-banked-setups.patch" diff --git a/a/2.txt b/a/2.txt deleted file mode 100644 index 5061bf2..0000000 --- a/a/2.txt +++ /dev/null @@ -1,316 +0,0 @@ ->From da57c3979543fcef47f1ae22b5224a1d7a96aa2d Mon Sep 17 00:00:00 2001 -From: Marc Zyngier <marc.zyngier@arm.com> -Date: Fri, 7 Oct 2011 10:23:31 +0100 -Subject: [PATCH] ARM: gic: allow GIC to support non-banked setups - -The GIC support code is heavily using the fact that hardware -implementations are exposing banked registers. Unfortunately, it -looks like at least one GIC implementation (EXYNOS4) offers both -the distributor and the CPU interfaces at different addresses, -depending on the CPU. - -This problem is solved by turning the distributor and CPU interface -addresses into per-cpu variables. The EXYNOS4 code is updated not -to mess with the GIC internals while handling interrupts, and -struct gic_chip_data is back to being private. - -Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> ---- - arch/arm/common/gic.c | 76 +++++++++++++++++++++++++++-------- - arch/arm/include/asm/hardware/gic.h | 17 +------ - arch/arm/mach-exynos4/cpu.c | 14 ------ - arch/arm/mach-exynos4/platsmp.c | 28 ++----------- - 4 files changed, 66 insertions(+), 69 deletions(-) - -diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c -index b574931..c7521dd 100644 ---- a/arch/arm/common/gic.c -+++ b/arch/arm/common/gic.c -@@ -37,6 +37,20 @@ - #include <asm/mach/irq.h> - #include <asm/hardware/gic.h> - -+struct gic_chip_data { -+ unsigned int irq_offset; -+ void __percpu __iomem **dist_base; -+ void __percpu __iomem **cpu_base; -+#ifdef CONFIG_CPU_PM -+ u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; -+ u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; -+ u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; -+ u32 __percpu *saved_ppi_enable; -+ u32 __percpu *saved_ppi_conf; -+#endif -+ unsigned int gic_irqs; -+}; -+ - static DEFINE_RAW_SPINLOCK(irq_controller_lock); - - /* Address of GIC 0 CPU interface */ -@@ -61,16 +75,26 @@ struct irq_chip gic_arch_extn = { - - static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; - -+static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) -+{ -+ return *__this_cpu_ptr(data->dist_base); -+} -+ - static inline void __iomem *gic_dist_base(struct irq_data *d) - { - struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); -- return gic_data->dist_base; -+ return gic_data_dist_base(gic_data); -+} -+ -+static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) -+{ -+ return *__this_cpu_ptr(data->cpu_base); - } - - static inline void __iomem *gic_cpu_base(struct irq_data *d) - { - struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); -- return gic_data->cpu_base; -+ return gic_data_cpu_base(gic_data); - } - - static inline unsigned int gic_irq(struct irq_data *d) -@@ -243,7 +267,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) - chained_irq_enter(chip, desc); - - raw_spin_lock(&irq_controller_lock); -- status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK); -+ status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); - raw_spin_unlock(&irq_controller_lock); - - gic_irq = (status & 0x3ff); -@@ -287,7 +311,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic, - { - unsigned int gic_irqs, irq_limit, i; - u32 cpumask; -- void __iomem *base = gic->dist_base; -+ void __iomem *base = gic_data_dist_base(gic); - u32 cpu = 0; - u32 nrppis = 0, ppi_base = 0; - -@@ -380,8 +404,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic, - - static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) - { -- void __iomem *dist_base = gic->dist_base; -- void __iomem *base = gic->cpu_base; -+ void __iomem *dist_base = gic_data_dist_base(gic); -+ void __iomem *base = gic_data_cpu_base(gic); - int i; - - /* -@@ -418,7 +442,7 @@ static void gic_dist_save(unsigned int gic_nr) - BUG(); - - gic_irqs = gic_data[gic_nr].gic_irqs; -- dist_base = gic_data[gic_nr].dist_base; -+ dist_base = gic_data_dist_base(&gic_data[gic_nr]); - - if (!dist_base) - return; -@@ -453,7 +477,7 @@ static void gic_dist_restore(unsigned int gic_nr) - BUG(); - - gic_irqs = gic_data[gic_nr].gic_irqs; -- dist_base = gic_data[gic_nr].dist_base; -+ dist_base = gic_data_dist_base(&gic_data[gic_nr]); - - if (!dist_base) - return; -@@ -489,8 +513,8 @@ static void gic_cpu_save(unsigned int gic_nr) - if (gic_nr >= MAX_GIC_NR) - BUG(); - -- dist_base = gic_data[gic_nr].dist_base; -- cpu_base = gic_data[gic_nr].cpu_base; -+ dist_base = gic_data_dist_base(&gic_data[gic_nr]); -+ cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); - - if (!dist_base || !cpu_base) - return; -@@ -515,8 +539,8 @@ static void gic_cpu_restore(unsigned int gic_nr) - if (gic_nr >= MAX_GIC_NR) - BUG(); - -- dist_base = gic_data[gic_nr].dist_base; -- cpu_base = gic_data[gic_nr].cpu_base; -+ dist_base = gic_data_dist_base(&gic_data[gic_nr]); -+ cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); - - if (!dist_base || !cpu_base) - return; -@@ -588,12 +612,24 @@ void __init gic_init(unsigned int gic_nr, unsigned int irq_start, - void __iomem *dist_base, void __iomem *cpu_base) - { - struct gic_chip_data *gic; -+ int cpu; - - BUG_ON(gic_nr >= MAX_GIC_NR); - - gic = &gic_data[gic_nr]; -- gic->dist_base = dist_base; -- gic->cpu_base = cpu_base; -+ gic->dist_base = alloc_percpu(void __iomem *); -+ gic->cpu_base = alloc_percpu(void __iomem *); -+ if (WARN_ON(!gic->dist_base || !gic->cpu_base)) { -+ free_percpu(gic->dist_base); -+ free_percpu(gic->cpu_base); -+ return; -+ } -+ -+ for_each_possible_cpu(cpu) { -+ *per_cpu_ptr(gic->dist_base, cpu) = dist_base; -+ *per_cpu_ptr(gic->cpu_base, cpu) = cpu_base; -+ } -+ - gic->irq_offset = (irq_start - 1) & ~31; - - if (gic_nr == 0) -@@ -605,11 +641,17 @@ void __init gic_init(unsigned int gic_nr, unsigned int irq_start, - gic_pm_init(gic); - } - --void __cpuinit gic_secondary_init(unsigned int gic_nr) -+void __cpuinit gic_secondary_init_base(unsigned int gic_nr, -+ void __iomem *dist_base, -+ void __iomem *cpu_base) - { - BUG_ON(gic_nr >= MAX_GIC_NR); - -- gic_cpu_init(&gic_data[gic_nr]); -+ if (dist_base) -+ *__this_cpu_ptr(gic_data[gic_nr].dist_base) = dist_base; -+ if (cpu_base) -+ *__this_cpu_ptr(gic_data[gic_nr].cpu_base) = cpu_base; -+ gic_cpu_init(&gic_data[gic_nr]); - } - - #ifdef CONFIG_SMP -@@ -629,6 +671,6 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) - dsb(); - - /* this always happens on GIC0 */ -- writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); -+ writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); - } - #endif -diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h -index 2b7ec2b..d45d78b 100644 ---- a/arch/arm/include/asm/hardware/gic.h -+++ b/arch/arm/include/asm/hardware/gic.h -@@ -36,24 +36,13 @@ - extern struct irq_chip gic_arch_extn; - - void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); --void gic_secondary_init(unsigned int); -+void gic_secondary_init_base(unsigned int, void __iomem *, void __iomem *); - void gic_handle_irq(struct pt_regs *regs); - void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); - void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); - --struct gic_chip_data { -- unsigned int irq_offset; -- void __iomem *dist_base; -- void __iomem *cpu_base; --#ifdef CONFIG_CPU_PM -- u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; -- u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; -- u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; -- u32 __percpu *saved_ppi_enable; -- u32 __percpu *saved_ppi_conf; --#endif -- unsigned int gic_irqs; --}; -+#define gic_secondary_init(n) gic_secondary_init_base((n), NULL, NULL) -+ - #endif - - #endif -diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c -index c682887..09e2760 100644 ---- a/arch/arm/mach-exynos4/cpu.c -+++ b/arch/arm/mach-exynos4/cpu.c -@@ -204,17 +204,6 @@ void __init exynos4_init_clocks(int xtal) - exynos4_setup_clocks(); - } - --static void exynos4_gic_irq_fix_base(struct irq_data *d) --{ -- struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); -- -- gic_data->cpu_base = S5P_VA_GIC_CPU + -- (gic_bank_offset * smp_processor_id()); -- -- gic_data->dist_base = S5P_VA_GIC_DIST + -- (gic_bank_offset * smp_processor_id()); --} -- - void __init exynos4_init_irq(void) - { - int irq; -@@ -222,9 +211,6 @@ void __init exynos4_init_irq(void) - gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; - - gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); -- gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base; -- gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base; -- gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base; - - for (irq = 0; irq < MAX_COMBINER_NR; irq++) { - -diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c -index 56377d2..76cb2ba 100644 ---- a/arch/arm/mach-exynos4/platsmp.c -+++ b/arch/arm/mach-exynos4/platsmp.c -@@ -67,39 +67,19 @@ static void __iomem *scu_base_addr(void) - - static DEFINE_SPINLOCK(boot_lock); - --static void __cpuinit exynos4_gic_secondary_init(void) -+static void __cpuinit exynos4_secondary_init(unsigned int cpu) - { - void __iomem *dist_base = S5P_VA_GIC_DIST + -- (gic_bank_offset * smp_processor_id()); -+ (gic_bank_offset * cpu_logical_map(cpu)); - void __iomem *cpu_base = S5P_VA_GIC_CPU + -- (gic_bank_offset * smp_processor_id()); -- int i; -- -- /* -- * Deal with the banked PPI and SGI interrupts - disable all -- * PPI interrupts, ensure all SGI interrupts are enabled. -- */ -- __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); -- __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); -+ (gic_bank_offset * cpu_logical_map(cpu)); - - /* -- * Set priority on PPI and SGI interrupts -- */ -- for (i = 0; i < 32; i += 4) -- __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); -- -- __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK); -- __raw_writel(1, cpu_base + GIC_CPU_CTRL); --} -- --static void __cpuinit exynos4_secondary_init(unsigned int cpu) --{ -- /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ -- exynos4_gic_secondary_init(); -+ gic_secondary_init_base(0, dist_base, cpu_base); - - /* - * let the primary processor know we're out of the --- -1.7.0.4 diff --git a/a/content_digest b/N1/content_digest index f0d379e..560f6e2 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,18 +3,11 @@ "ref\04E8C61C4.9090709@arm.com\0" "ref\000ec01cc83f1$81f84430$85e8cc90$%kim@samsung.com\0" "ref\04E8D645D.4020601@arm.com\0" - "From\0Marc Zyngier <marc.zyngier@arm.com>\0" - "Subject\0Re: [PATCH 5/7] ARM: EXYNOS4: Add support external GIC\0" + "From\0marc.zyngier@arm.com (Marc Zyngier)\0" + "Subject\0[PATCH 5/7] ARM: EXYNOS4: Add support external GIC\0" "Date\0Fri, 07 Oct 2011 10:44:59 +0100\0" - "To\0Kukjin Kim <kgene.kim@samsung.com>\0" - "Cc\0linux-samsung-soc@vger.kernel.org <linux-samsung-soc@vger.kernel.org>" - 'Arnd Bergmann' <arnd@arndb.de> - Will Deacon <Will.Deacon@arm.com> - ben-linux@fluff.org <ben-linux@fluff.org> - 'Russell King' <rmk+kernel@arm.linux.org.uk> - 'Changhwan Youn' <chaos.youn@samsung.com> - " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "On 06/10/11 09:18, Marc Zyngier wrote:\n" "> On 06/10/11 07:30, Kukjin Kim wrote:\n" @@ -130,324 +123,5 @@ "\tM.\n" "-- \n" Jazz is not dead. It just smells funny... - "\01:2\0" - "fn\00001-ARM-gic-allow-GIC-to-support-non-banked-setups.patch\0" - "b\0" - ">From da57c3979543fcef47f1ae22b5224a1d7a96aa2d Mon Sep 17 00:00:00 2001\n" - "From: Marc Zyngier <marc.zyngier@arm.com>\n" - "Date: Fri, 7 Oct 2011 10:23:31 +0100\n" - "Subject: [PATCH] ARM: gic: allow GIC to support non-banked setups\n" - "\n" - "The GIC support code is heavily using the fact that hardware\n" - "implementations are exposing banked registers. Unfortunately, it\n" - "looks like at least one GIC implementation (EXYNOS4) offers both\n" - "the distributor and the CPU interfaces at different addresses,\n" - "depending on the CPU.\n" - "\n" - "This problem is solved by turning the distributor and CPU interface\n" - "addresses into per-cpu variables. The EXYNOS4 code is updated not\n" - "to mess with the GIC internals while handling interrupts, and\n" - "struct gic_chip_data is back to being private.\n" - "\n" - "Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>\n" - "---\n" - " arch/arm/common/gic.c | 76 +++++++++++++++++++++++++++--------\n" - " arch/arm/include/asm/hardware/gic.h | 17 +------\n" - " arch/arm/mach-exynos4/cpu.c | 14 ------\n" - " arch/arm/mach-exynos4/platsmp.c | 28 ++-----------\n" - " 4 files changed, 66 insertions(+), 69 deletions(-)\n" - "\n" - "diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c\n" - "index b574931..c7521dd 100644\n" - "--- a/arch/arm/common/gic.c\n" - "+++ b/arch/arm/common/gic.c\n" - "@@ -37,6 +37,20 @@\n" - " #include <asm/mach/irq.h>\n" - " #include <asm/hardware/gic.h>\n" - " \n" - "+struct gic_chip_data {\n" - "+\tunsigned int irq_offset;\n" - "+\tvoid __percpu __iomem **dist_base;\n" - "+\tvoid __percpu __iomem **cpu_base;\n" - "+#ifdef CONFIG_CPU_PM\n" - "+\tu32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];\n" - "+\tu32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];\n" - "+\tu32 saved_spi_target[DIV_ROUND_UP(1020, 4)];\n" - "+\tu32 __percpu *saved_ppi_enable;\n" - "+\tu32 __percpu *saved_ppi_conf;\n" - "+#endif\n" - "+\tunsigned int gic_irqs;\n" - "+};\n" - "+\n" - " static DEFINE_RAW_SPINLOCK(irq_controller_lock);\n" - " \n" - " /* Address of GIC 0 CPU interface */\n" - "@@ -61,16 +75,26 @@ struct irq_chip gic_arch_extn = {\n" - " \n" - " static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;\n" - " \n" - "+static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)\n" - "+{\n" - "+\treturn *__this_cpu_ptr(data->dist_base);\n" - "+}\n" - "+\n" - " static inline void __iomem *gic_dist_base(struct irq_data *d)\n" - " {\n" - " \tstruct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);\n" - "-\treturn gic_data->dist_base;\n" - "+\treturn gic_data_dist_base(gic_data);\n" - "+}\n" - "+\n" - "+static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)\n" - "+{\n" - "+\treturn *__this_cpu_ptr(data->cpu_base);\n" - " }\n" - " \n" - " static inline void __iomem *gic_cpu_base(struct irq_data *d)\n" - " {\n" - " \tstruct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);\n" - "-\treturn gic_data->cpu_base;\n" - "+\treturn gic_data_cpu_base(gic_data);\n" - " }\n" - " \n" - " static inline unsigned int gic_irq(struct irq_data *d)\n" - "@@ -243,7 +267,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)\n" - " \tchained_irq_enter(chip, desc);\n" - " \n" - " \traw_spin_lock(&irq_controller_lock);\n" - "-\tstatus = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);\n" - "+\tstatus = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);\n" - " \traw_spin_unlock(&irq_controller_lock);\n" - " \n" - " \tgic_irq = (status & 0x3ff);\n" - "@@ -287,7 +311,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic,\n" - " {\n" - " \tunsigned int gic_irqs, irq_limit, i;\n" - " \tu32 cpumask;\n" - "-\tvoid __iomem *base = gic->dist_base;\n" - "+\tvoid __iomem *base = gic_data_dist_base(gic);\n" - " \tu32 cpu = 0;\n" - " \tu32 nrppis = 0, ppi_base = 0;\n" - " \n" - "@@ -380,8 +404,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic,\n" - " \n" - " static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)\n" - " {\n" - "-\tvoid __iomem *dist_base = gic->dist_base;\n" - "-\tvoid __iomem *base = gic->cpu_base;\n" - "+\tvoid __iomem *dist_base = gic_data_dist_base(gic);\n" - "+\tvoid __iomem *base = gic_data_cpu_base(gic);\n" - " \tint i;\n" - " \n" - " \t/*\n" - "@@ -418,7 +442,7 @@ static void gic_dist_save(unsigned int gic_nr)\n" - " \t\tBUG();\n" - " \n" - " \tgic_irqs = gic_data[gic_nr].gic_irqs;\n" - "-\tdist_base = gic_data[gic_nr].dist_base;\n" - "+\tdist_base = gic_data_dist_base(&gic_data[gic_nr]);\n" - " \n" - " \tif (!dist_base)\n" - " \t\treturn;\n" - "@@ -453,7 +477,7 @@ static void gic_dist_restore(unsigned int gic_nr)\n" - " \t\tBUG();\n" - " \n" - " \tgic_irqs = gic_data[gic_nr].gic_irqs;\n" - "-\tdist_base = gic_data[gic_nr].dist_base;\n" - "+\tdist_base = gic_data_dist_base(&gic_data[gic_nr]);\n" - " \n" - " \tif (!dist_base)\n" - " \t\treturn;\n" - "@@ -489,8 +513,8 @@ static void gic_cpu_save(unsigned int gic_nr)\n" - " \tif (gic_nr >= MAX_GIC_NR)\n" - " \t\tBUG();\n" - " \n" - "-\tdist_base = gic_data[gic_nr].dist_base;\n" - "-\tcpu_base = gic_data[gic_nr].cpu_base;\n" - "+\tdist_base = gic_data_dist_base(&gic_data[gic_nr]);\n" - "+\tcpu_base = gic_data_cpu_base(&gic_data[gic_nr]);\n" - " \n" - " \tif (!dist_base || !cpu_base)\n" - " \t\treturn;\n" - "@@ -515,8 +539,8 @@ static void gic_cpu_restore(unsigned int gic_nr)\n" - " \tif (gic_nr >= MAX_GIC_NR)\n" - " \t\tBUG();\n" - " \n" - "-\tdist_base = gic_data[gic_nr].dist_base;\n" - "-\tcpu_base = gic_data[gic_nr].cpu_base;\n" - "+\tdist_base = gic_data_dist_base(&gic_data[gic_nr]);\n" - "+\tcpu_base = gic_data_cpu_base(&gic_data[gic_nr]);\n" - " \n" - " \tif (!dist_base || !cpu_base)\n" - " \t\treturn;\n" - "@@ -588,12 +612,24 @@ void __init gic_init(unsigned int gic_nr, unsigned int irq_start,\n" - " \tvoid __iomem *dist_base, void __iomem *cpu_base)\n" - " {\n" - " \tstruct gic_chip_data *gic;\n" - "+\tint cpu;\n" - " \n" - " \tBUG_ON(gic_nr >= MAX_GIC_NR);\n" - " \n" - " \tgic = &gic_data[gic_nr];\n" - "-\tgic->dist_base = dist_base;\n" - "-\tgic->cpu_base = cpu_base;\n" - "+\tgic->dist_base = alloc_percpu(void __iomem *);\n" - "+\tgic->cpu_base = alloc_percpu(void __iomem *);\n" - "+\tif (WARN_ON(!gic->dist_base || !gic->cpu_base)) {\n" - "+\t\tfree_percpu(gic->dist_base);\n" - "+\t\tfree_percpu(gic->cpu_base);\n" - "+\t\treturn;\n" - "+\t}\n" - "+\n" - "+\tfor_each_possible_cpu(cpu) {\n" - "+\t\t*per_cpu_ptr(gic->dist_base, cpu) = dist_base;\n" - "+\t\t*per_cpu_ptr(gic->cpu_base, cpu) = cpu_base;\n" - "+\t}\n" - "+\n" - " \tgic->irq_offset = (irq_start - 1) & ~31;\n" - " \n" - " \tif (gic_nr == 0)\n" - "@@ -605,11 +641,17 @@ void __init gic_init(unsigned int gic_nr, unsigned int irq_start,\n" - " \tgic_pm_init(gic);\n" - " }\n" - " \n" - "-void __cpuinit gic_secondary_init(unsigned int gic_nr)\n" - "+void __cpuinit gic_secondary_init_base(unsigned int gic_nr,\n" - "+\t\t\t\t void __iomem *dist_base,\n" - "+\t\t\t\t void __iomem *cpu_base)\n" - " {\n" - " \tBUG_ON(gic_nr >= MAX_GIC_NR);\n" - " \n" - "-\tgic_cpu_init(&gic_data[gic_nr]);\n" - "+\tif (dist_base)\n" - "+\t\t*__this_cpu_ptr(gic_data[gic_nr].dist_base) = dist_base;\n" - "+\tif (cpu_base)\n" - "+\t\t*__this_cpu_ptr(gic_data[gic_nr].cpu_base) = cpu_base;\n" - "+\tgic_cpu_init(&gic_data[gic_nr]);\t\n" - " }\n" - " \n" - " #ifdef CONFIG_SMP\n" - "@@ -629,6 +671,6 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)\n" - " \tdsb();\n" - " \n" - " \t/* this always happens on GIC0 */\n" - "-\twritel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);\n" - "+\twritel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);\n" - " }\n" - " #endif\n" - "diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h\n" - "index 2b7ec2b..d45d78b 100644\n" - "--- a/arch/arm/include/asm/hardware/gic.h\n" - "+++ b/arch/arm/include/asm/hardware/gic.h\n" - "@@ -36,24 +36,13 @@\n" - " extern struct irq_chip gic_arch_extn;\n" - " \n" - " void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);\n" - "-void gic_secondary_init(unsigned int);\n" - "+void gic_secondary_init_base(unsigned int, void __iomem *, void __iomem *);\n" - " void gic_handle_irq(struct pt_regs *regs);\n" - " void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);\n" - " void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);\n" - " \n" - "-struct gic_chip_data {\n" - "-\tunsigned int irq_offset;\n" - "-\tvoid __iomem *dist_base;\n" - "-\tvoid __iomem *cpu_base;\n" - "-#ifdef CONFIG_CPU_PM\n" - "-\tu32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];\n" - "-\tu32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];\n" - "-\tu32 saved_spi_target[DIV_ROUND_UP(1020, 4)];\n" - "-\tu32 __percpu *saved_ppi_enable;\n" - "-\tu32 __percpu *saved_ppi_conf;\n" - "-#endif\n" - "-\tunsigned int gic_irqs;\n" - "-};\n" - "+#define gic_secondary_init(n)\tgic_secondary_init_base((n), NULL, NULL)\n" - "+\n" - " #endif\n" - " \n" - " #endif\n" - "diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c\n" - "index c682887..09e2760 100644\n" - "--- a/arch/arm/mach-exynos4/cpu.c\n" - "+++ b/arch/arm/mach-exynos4/cpu.c\n" - "@@ -204,17 +204,6 @@ void __init exynos4_init_clocks(int xtal)\n" - " \texynos4_setup_clocks();\n" - " }\n" - " \n" - "-static void exynos4_gic_irq_fix_base(struct irq_data *d)\n" - "-{\n" - "-\tstruct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);\n" - "-\n" - "-\tgic_data->cpu_base = S5P_VA_GIC_CPU +\n" - "-\t\t\t (gic_bank_offset * smp_processor_id());\n" - "-\n" - "-\tgic_data->dist_base = S5P_VA_GIC_DIST +\n" - "-\t\t\t (gic_bank_offset * smp_processor_id());\n" - "-}\n" - "-\n" - " void __init exynos4_init_irq(void)\n" - " {\n" - " \tint irq;\n" - "@@ -222,9 +211,6 @@ void __init exynos4_init_irq(void)\n" - " \tgic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;\n" - " \n" - " \tgic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);\n" - "-\tgic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;\n" - "-\tgic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;\n" - "-\tgic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;\n" - " \n" - " \tfor (irq = 0; irq < MAX_COMBINER_NR; irq++) {\n" - " \n" - "diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c\n" - "index 56377d2..76cb2ba 100644\n" - "--- a/arch/arm/mach-exynos4/platsmp.c\n" - "+++ b/arch/arm/mach-exynos4/platsmp.c\n" - "@@ -67,39 +67,19 @@ static void __iomem *scu_base_addr(void)\n" - " \n" - " static DEFINE_SPINLOCK(boot_lock);\n" - " \n" - "-static void __cpuinit exynos4_gic_secondary_init(void)\n" - "+static void __cpuinit exynos4_secondary_init(unsigned int cpu)\n" - " {\n" - " \tvoid __iomem *dist_base = S5P_VA_GIC_DIST +\n" - "-\t\t\t\t(gic_bank_offset * smp_processor_id());\n" - "+\t\t\t\t(gic_bank_offset * cpu_logical_map(cpu));\n" - " \tvoid __iomem *cpu_base = S5P_VA_GIC_CPU +\n" - "-\t\t\t\t(gic_bank_offset * smp_processor_id());\n" - "-\tint i;\n" - "-\n" - "-\t/*\n" - "-\t * Deal with the banked PPI and SGI interrupts - disable all\n" - "-\t * PPI interrupts, ensure all SGI interrupts are enabled.\n" - "-\t */\n" - "-\t__raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);\n" - "-\t__raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);\n" - "+\t\t\t\t(gic_bank_offset * cpu_logical_map(cpu));\n" - " \n" - " \t/*\n" - "-\t * Set priority on PPI and SGI interrupts\n" - "-\t */\n" - "-\tfor (i = 0; i < 32; i += 4)\n" - "-\t\t__raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);\n" - "-\n" - "-\t__raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);\n" - "-\t__raw_writel(1, cpu_base + GIC_CPU_CTRL);\n" - "-}\n" - "-\n" - "-static void __cpuinit exynos4_secondary_init(unsigned int cpu)\n" - "-{\n" - "-\t/*\n" - " \t * if any interrupts are already enabled for the primary\n" - " \t * core (e.g. timer irq), then they will not have been enabled\n" - " \t * for us: do so\n" - " \t */\n" - "-\texynos4_gic_secondary_init();\n" - "+\tgic_secondary_init_base(0, dist_base, cpu_base);\n" - " \n" - " \t/*\n" - " \t * let the primary processor know we're out of the\n" - "-- \n" - 1.7.0.4 -60bf5211a2f79769df9ef989f70bcebcc7ca04c5ed322186232a19ccedee7987 +d50a50f1232aa90ee6a0299750b80cb10b4394440bd60290d3ad3afb4a7e273b
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.