From: Richard Henderson <rth@twiddle.net>
To: khansa@kics.edu.pk
Cc: peter.maydell@linaro.org, andreas.faerber@web.de,
riku.voipio@iki.fi, qemu-devel@nongnu.org, aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH v2 5/6] target-mips: Support for Cavium specific instructions
Date: Fri, 21 Oct 2011 07:25:35 -0700 [thread overview]
Message-ID: <4EA180DF.7010101@twiddle.net> (raw)
In-Reply-To: <1319185026-17589-6-git-send-email-khansa@kics.edu.pk>
On 10/21/2011 01:17 AM, khansa@kics.edu.pk wrote:
> + switch (opc) {
> + case OPC_SEQ:
> + tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rd], t0, 1);
> + opn = "seq";
> + break;
> + case OPC_SNE:
> + tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_gpr[rd], t0, 0);
> + opn = "sne";
If you keep posting the same un-fixed patch set, pretty soon
no one's going to pay any attention to you whatsoever.
r~
next prev parent reply other threads:[~2011-10-21 14:25 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-21 8:17 [Qemu-devel] [PATCH v2 0/6] MIPS64 user mode emulation in QEMU with Cavium specific instruction support khansa
2011-10-21 8:17 ` [Qemu-devel] [PATCH v2 1/6] linux-user:Support for MIPS64 user mode emulation in QEMU khansa
2011-10-21 8:17 ` [Qemu-devel] [PATCH v2 2/6] target-mips:enabling of 64 bit user mode and floating point operations khansa
2011-10-21 8:17 ` [Qemu-devel] [PATCH v2 3/6] linux-user:Signal handling for MIPS64 khansa
2011-10-21 8:17 ` [Qemu-devel] [PATCH v2 4/6] target-mips:Octeon cpu definition khansa
2011-10-21 8:17 ` [Qemu-devel] [PATCH v2 5/6] target-mips: Support for Cavium specific instructions khansa
2011-10-21 14:25 ` Richard Henderson [this message]
2011-10-21 8:17 ` [Qemu-devel] [PATCH v2 6/6] Addition of Cavium instructions in disassembler khansa
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