From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:35318) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RHXod-00005V-D4 for qemu-devel@nongnu.org; Sat, 22 Oct 2011 05:24:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RHXoc-00061V-5O for qemu-devel@nongnu.org; Sat, 22 Oct 2011 05:24:31 -0400 Received: from fmmailgate04.web.de ([217.72.192.242]:32787) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RHXob-0005yf-Qy for qemu-devel@nongnu.org; Sat, 22 Oct 2011 05:24:30 -0400 Message-ID: <4EA28B68.60804@web.de> Date: Sat, 22 Oct 2011 11:22:48 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1317581808-9784-1-git-send-email-andreas.faerber@web.de> <1317637971-19296-1-git-send-email-andreas.faerber@web.de> In-Reply-To: <1317637971-19296-1-git-send-email-andreas.faerber@web.de> Content-Type: text/plain; charset=UTF-8 Sender: andreas.faerber@web.de Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] target-arm: Tidy up ARM1136 CPUID naming List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andrzej Zaborowski , Peter Maydell Cc: qemu-devel@nongnu.org Am 03.10.2011 12:32, schrieb Andreas F=C3=A4rber: > -cpu arm1136-r2 is commented to in fact be ARM1136 r0p2, whereas > -cpu arm1136 seems to be ARM1136 r1p3 according to the MIDR value. >=20 > The CPUID values contain major and minor revision numbers (rnpn) and > are never used with a mask, so are specific to the chosen revision. > Rename the CPUID preprocessor defines to reflect this, but leave the > CPU model names unchanged for command line compatibility. >=20 > Cc: Andrzej Zaborowski > Cc: Peter Maydell > Signed-off-by: Andreas F=C3=A4rber > --- Ping? Andreas > target-arm/cpu.h | 4 ++-- > target-arm/helper.c | 12 ++++++------ > 2 files changed, 8 insertions(+), 8 deletions(-) >=20 > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 6ab780d..783989f 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -419,8 +419,8 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, > #define ARM_CPUID_PXA270_B1 0x69054113 > #define ARM_CPUID_PXA270_C0 0x69054114 > #define ARM_CPUID_PXA270_C5 0x69054117 > -#define ARM_CPUID_ARM1136 0x4117b363 > -#define ARM_CPUID_ARM1136_R2 0x4107b362 > +#define ARM_CPUID_ARM1136_R1P3 0x4117b363 > +#define ARM_CPUID_ARM1136_R0P2 0x4107b362 > #define ARM_CPUID_ARM1176 0x410fb767 > #define ARM_CPUID_ARM11MPCORE 0x410fb022 > #define ARM_CPUID_CORTEXA8 0x410fc080 > diff --git a/target-arm/helper.c b/target-arm/helper.c > index e2428eb..0d342ba 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -76,11 +76,11 @@ static void cpu_reset_model_id(CPUARMState *env, ui= nt32_t id) > env->cp15.c0_cachetype =3D 0x1dd20d2; > env->cp15.c1_sys =3D 0x00090078; > break; > - case ARM_CPUID_ARM1136: > + case ARM_CPUID_ARM1136_R1P3: > /* This is the 1136 r1, which is a v6K core */ > set_feature(env, ARM_FEATURE_V6K); > /* Fall through */ > - case ARM_CPUID_ARM1136_R2: > + case ARM_CPUID_ARM1136_R0P2: > /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie = an > * older core than plain "arm1136". In particular this does no= t > * have the v6K features. > @@ -417,8 +417,8 @@ static const struct arm_cpu_t arm_cpu_names[] =3D { > { ARM_CPUID_ARM926, "arm926"}, > { ARM_CPUID_ARM946, "arm946"}, > { ARM_CPUID_ARM1026, "arm1026"}, > - { ARM_CPUID_ARM1136, "arm1136"}, > - { ARM_CPUID_ARM1136_R2, "arm1136-r2"}, > + { ARM_CPUID_ARM1136_R1P3, "arm1136" }, > + { ARM_CPUID_ARM1136_R0P2, "arm1136-r2" }, > { ARM_CPUID_ARM1176, "arm1176"}, > { ARM_CPUID_ARM11MPCORE, "arm11mpcore"}, > { ARM_CPUID_CORTEXM3, "cortex-m3"}, > @@ -1886,8 +1886,8 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t= insn) > switch (ARM_CPUID(env)) { > case ARM_CPUID_ARM1026: > return 1; > - case ARM_CPUID_ARM1136: > - case ARM_CPUID_ARM1136_R2: > + case ARM_CPUID_ARM1136_R1P3: > + case ARM_CPUID_ARM1136_R0P2: > case ARM_CPUID_ARM1176: > return 7; > case ARM_CPUID_ARM11MPCORE: