From: Peter Barada <peter.barada@gmail.com>
To: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Peter Barada <peter.barada@logicpd.com>,
Ashwin Bihari <abihari@gmail.com>,
"linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>
Subject: Re: Linux 3.0 DSS support
Date: Wed, 02 Nov 2011 11:42:23 -0400 [thread overview]
Message-ID: <4EB164DF.506@gmail.com> (raw)
In-Reply-To: <1319528229.1684.20.camel@lappyti>
On 10/25/2011 03:37 AM, Tomi Valkeinen wrote:
> Hi,
>
> On Mon, 2011-10-24 at 13:55 -0400, Peter Barada wrote:
>> In the above case (and my case where I'm looking for a 9Mhz pixel
>> clock), fck_div is calculated at higher than 16 - and the video
>> output
>> is wrong (i.e. no pixel clock and hsync runs at 32x the requested
>> rate).
> DM37x TRM says:
>
> "DSS1_ALWON_FCLK: Issued from DPLL4. Its frequency can be a division by
> 1 to 16 of the frequency of the DPLL4 synthesized clock."
>
> I take it that DM37x is detected as cpu_is_3630()?
>
> The DSS driver currently handles only OMAPs, so for other SoCs the
> driver may contain lots of bugs like this.
Yes, cpu_is_omap3630() returns true on a DM3730. I'll rework the patch
(I think all that is needed is to drop the "cpu_is_omap3630() ||" from
the test - then fck_div_max will remain at 16 for the DM3730.
--
Peter Barada
peter.barada@gmail.com
next prev parent reply other threads:[~2011-11-02 15:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CANLagX8WaHGkqOZ2UnLR1ihOABbdDy1ZAyW19yO=f-JNUaLKfw@mail.gmail.com>
2011-10-17 7:19 ` Linux 3.0 DSS support Tomi Valkeinen
[not found] ` <CANLagX9R9DKi1MCa11t4REDFzRgXdJQWxNG4Q6mv46f8dACdSQ@mail.gmail.com>
2011-10-19 13:27 ` Ashwin Bihari
2011-10-24 17:55 ` Peter Barada
2011-10-25 7:37 ` Tomi Valkeinen
2011-11-02 15:42 ` Peter Barada [this message]
2011-11-03 9:35 ` Koen Kooi
2011-11-03 9:46 ` Tomi Valkeinen
2011-11-03 14:50 ` Peter Barada
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