From: Anthony Liguori <anthony@codemonkey.ws>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH] hw/pxa2xx.c: Fix handling of R/WC bits in PMCR
Date: Fri, 11 Nov 2011 13:45:34 -0600 [thread overview]
Message-ID: <4EBD7B5E.8070607@codemonkey.ws> (raw)
In-Reply-To: <1320871595-10304-1-git-send-email-peter.maydell@linaro.org>
On 11/09/2011 02:46 PM, Peter Maydell wrote:
> Fix a bug in handling the write-one-to-clear bits in the PMCR
> which meant that we would always clear the bit even if the
> value written was a zero. Spotted by Coverity (see bug 887883).
>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
Applied. Thanks.
Regards,
Anthony Liguori
> ---
> hw/pxa2xx.c | 4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
>
> diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
> index bfc28a9..d38b922 100644
> --- a/hw/pxa2xx.c
> +++ b/hw/pxa2xx.c
> @@ -114,7 +114,9 @@ static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
>
> switch (addr) {
> case PMCR:
> - s->pm_regs[addr>> 2]&= 0x15& ~(value& 0x2a);
> + /* Clear the write-one-to-clear bits... */
> + s->pm_regs[addr>> 2]&= ~(value& 0x2a);
> + /* ...and set the plain r/w bits */
> s->pm_regs[addr>> 2] |= value& 0x15;
> break;
>
next prev parent reply other threads:[~2011-11-11 19:45 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-11-09 20:46 [Qemu-devel] [PATCH] hw/pxa2xx.c: Fix handling of R/WC bits in PMCR Peter Maydell
2011-11-11 19:45 ` Anthony Liguori [this message]
2011-11-11 21:05 ` andrzej zaborowski
2011-11-11 23:20 ` Peter Maydell
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