diff for duplicates of <4EBDA1FB.9040800@gmail.com> diff --git a/a/1.txt b/N1/1.txt index d45ac5b..260ab69 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -8,7 +8,7 @@ On 11/11/2011 12:27 PM, Pawel Moll wrote: > implementation of the DT machine support (this code is separate > from the current core tile code). > -> Signed-off-by: Pawel Moll <pawel.moll@arm.com> +> Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> > --- > arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 132 ++++++++++++++++++++++++++++ > arch/arm/boot/dts/vexpress-v2p-ca9.dts | 146 +++++++++++++++++++++++++++++++ @@ -55,25 +55,25 @@ On 11/11/2011 12:27 PM, Pawel Moll wrote: > + timer = &mb_timer01; > + }; > + -> + memory at 80000000 { +> + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x40000000>; > + }; > + -> + hdlcd at 2a110000 { +> + hdlcd@2a110000 { > + compatible = "arm,hdlcd"; > + reg = <0x2a110000 0x1000>; > + interrupts = <0 85 4>; > + }; > + -> + dmc at 2a150000 { +> + dmc@2a150000 { I missed this earlier, but the preferred generic name is "memory-controller" > + compatible = "arm,pl341", "arm,primecell"; > + reg = <0x2a150000 0x1000>; > + }; > + -> + smc at 2a190000 { +> + smc@2a190000 { same here. @@ -83,7 +83,7 @@ same here. > + <0 87 4>; > + }; > + -> + gic: interrupt-controller at 2c001000 { +> + gic: interrupt-controller@2c001000 { > + compatible = "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; @@ -92,7 +92,7 @@ same here. > + <0x2c000100 0x100>; > + }; > + -> + L2: cache-controller at 2c0f0000 { +> + L2: cache-controller@2c0f0000 { > + compatible = "arm,pl310-cache"; > + reg = <0x2c0f0000 0x1000>; > + interrupts = <0 84 4>; @@ -198,43 +198,43 @@ same here. > + timer = &mb_timer01; > + }; > + -> + memory at 60000000 { +> + memory@60000000 { > + device_type = "memory"; > + reg = <0x60000000 0x40000000>; > + }; > + -> + clcd at 10020000 { +> + clcd@10020000 { > + compatible = "arm,pl111", "arm,primecell"; > + reg = <0x10020000 0x1000>; > + interrupts = <0 44 4>; > + }; > + -> + dmc at 100e0000 { +> + dmc@100e0000 { > + compatible = "arm,pl341", "arm,primecell"; > + reg = <0x100e0000 0x1000>; > + }; > + -> + smc at 100e1000 { +> + smc@100e1000 { > + compatible = "arm,pl354", "arm,primecell"; > + reg = <0x100e1000 0x1000>; > + interrupts = <0 45 4>, > + <0 46 4>; > + }; > + -> + timer at 100e4000 { +> + timer@100e4000 { > + compatible = "arm,sp804", "arm,primecell"; > + reg = <0x100e4000 0x1000>; > + interrupts = <0 48 4>, > + <0 49 4>; > + }; > + -> + watchdog at 100e5000 { +> + watchdog@100e5000 { > + compatible = "arm,sp805", "arm,primecell"; > + reg = <0x100e5000 0x1000>; > + interrupts = <0 51 4>; > + }; > + -> + gic: interrupt-controller at 1e001000 { +> + gic: interrupt-controller@1e001000 { > + compatible = "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; @@ -243,7 +243,7 @@ same here. > + <0x1e000100 0x100>; > + }; > + -> + L2: cache-controller at 1e00a000 { +> + L2: cache-controller@1e00a000 { > + compatible = "arm,pl310-cache"; > + reg = <0x1e00a000 0x1000>; > + interrupts = <0 43 4>; diff --git a/a/content_digest b/N1/content_digest index 92fd8ef..ba6da6b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,12 @@ "ref\01321036026-23411-1-git-send-email-pawel.moll@arm.com\0" "ref\01321036026-23411-6-git-send-email-pawel.moll@arm.com\0" - "From\0robherring2@gmail.com (Rob Herring)\0" - "Subject\0[PATCH 5/5] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4\0" + "ref\01321036026-23411-6-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org\0" + "From\0Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Subject\0Re: [PATCH 5/5] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4\0" "Date\0Fri, 11 Nov 2011 16:30:19 -0600\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>\0" + "Cc\0devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org" + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "Pawel,\n" @@ -16,7 +19,7 @@ "> implementation of the DT machine support (this code is separate\n" "> from the current core tile code).\n" "> \n" - "> Signed-off-by: Pawel Moll <pawel.moll@arm.com>\n" + "> Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>\n" "> ---\n" "> arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 132 ++++++++++++++++++++++++++++\n" "> arch/arm/boot/dts/vexpress-v2p-ca9.dts | 146 +++++++++++++++++++++++++++++++\n" @@ -63,25 +66,25 @@ "> +\t\ttimer = &mb_timer01;\n" "> +\t};\n" "> +\n" - "> +\tmemory at 80000000 {\n" + "> +\tmemory@80000000 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0x80000000 0x40000000>;\n" "> +\t};\n" "> +\n" - "> +\thdlcd at 2a110000 {\n" + "> +\thdlcd@2a110000 {\n" "> +\t\tcompatible = \"arm,hdlcd\";\n" "> +\t\treg = <0x2a110000 0x1000>;\n" "> +\t\tinterrupts = <0 85 4>;\n" "> +\t};\n" "> +\t\n" - "> +\tdmc at 2a150000 {\n" + "> +\tdmc@2a150000 {\n" "\n" "I missed this earlier, but the preferred generic name is \"memory-controller\"\n" "> +\t\tcompatible = \"arm,pl341\", \"arm,primecell\";\n" "> +\t\treg = <0x2a150000 0x1000>;\n" "> +\t};\n" "> +\n" - "> +\tsmc at 2a190000 {\n" + "> +\tsmc@2a190000 {\n" "\n" "same here.\n" "\n" @@ -91,7 +94,7 @@ "> +\t\t\t <0 87 4>;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 2c001000 {\n" + "> +\tgic: interrupt-controller@2c001000 {\n" "> +\t\tcompatible = \"arm,cortex-a9-gic\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <0>;\n" @@ -100,7 +103,7 @@ "> +\t\t <0x2c000100 0x100>;\n" "> +\t};\n" "> +\n" - "> +\tL2: cache-controller at 2c0f0000 {\n" + "> +\tL2: cache-controller@2c0f0000 {\n" "> +\t\tcompatible = \"arm,pl310-cache\";\n" "> +\t\treg = <0x2c0f0000 0x1000>;\n" "> +\t\tinterrupts = <0 84 4>;\n" @@ -206,43 +209,43 @@ "> +\t\ttimer = &mb_timer01;\n" "> +\t};\n" "> +\n" - "> +\tmemory at 60000000 {\n" + "> +\tmemory@60000000 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0x60000000 0x40000000>;\n" "> +\t};\n" "> +\n" - "> +\tclcd at 10020000 {\n" + "> +\tclcd@10020000 {\n" "> +\t\tcompatible = \"arm,pl111\", \"arm,primecell\";\n" "> +\t\treg = <0x10020000 0x1000>;\n" "> +\t\tinterrupts = <0 44 4>;\n" "> +\t};\n" "> +\n" - "> +\tdmc at 100e0000 {\n" + "> +\tdmc@100e0000 {\n" "> +\t\tcompatible = \"arm,pl341\", \"arm,primecell\";\n" "> +\t\treg = <0x100e0000 0x1000>;\n" "> +\t};\n" "> +\n" - "> +\tsmc at 100e1000 {\n" + "> +\tsmc@100e1000 {\n" "> +\t\tcompatible = \"arm,pl354\", \"arm,primecell\";\n" "> +\t\treg = <0x100e1000 0x1000>;\n" "> +\t\tinterrupts = <0 45 4>,\n" "> +\t\t\t <0 46 4>;\n" "> +\t};\n" "> +\n" - "> +\ttimer at 100e4000 {\n" + "> +\ttimer@100e4000 {\n" "> +\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n" "> +\t\treg = <0x100e4000 0x1000>;\n" "> +\t\tinterrupts = <0 48 4>,\n" "> +\t\t\t <0 49 4>;\n" "> +\t};\n" "> +\n" - "> +\twatchdog at 100e5000 {\n" + "> +\twatchdog@100e5000 {\n" "> +\t\tcompatible = \"arm,sp805\", \"arm,primecell\";\n" "> +\t\treg = <0x100e5000 0x1000>;\n" "> +\t\tinterrupts = <0 51 4>;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 1e001000 {\n" + "> +\tgic: interrupt-controller@1e001000 {\n" "> +\t\tcompatible = \"arm,cortex-a9-gic\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <0>;\n" @@ -251,7 +254,7 @@ "> +\t\t <0x1e000100 0x100>;\n" "> +\t};\n" "> +\n" - "> +\tL2: cache-controller at 1e00a000 {\n" + "> +\tL2: cache-controller@1e00a000 {\n" "> +\t\tcompatible = \"arm,pl310-cache\";\n" "> +\t\treg = <0x1e00a000 0x1000>;\n" "> +\t\tinterrupts = <0 43 4>;\n" @@ -474,4 +477,4 @@ "> +\t.dt_compat\t= v2p_ca5s_ca9_dt_match,\n" > +MACHINE_END -b3a357f1f8488778ed6c8470adc0f48c6c40be4bb6d5bacf3760e8c0b42dbc9f +35dc1d2f0827c4de2f1fee1436efbe1528b3b8cb31aa48f8cf0f02faf644113d
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.