From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ch1ehsobe001.messaging.microsoft.com ([216.32.181.181] helo=ch1outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1RTW53-0006oZ-53 for linux-mtd@lists.infradead.org; Thu, 24 Nov 2011 09:58:57 +0000 Message-ID: <4ECE162D.7080408@freescale.com> Date: Thu, 24 Nov 2011 18:02:21 +0800 From: LiuShuo MIME-Version: 1.0 To: Subject: Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to support large-page Nand chip References: <1322095306-13156-1-git-send-email-b35362@freescale.com> <1322095306-13156-3-git-send-email-b35362@freescale.com> <1322120515.24797.296.camel@sauron.fi.intel.com> <3F607A5180246847A760FD34122A1E052DC61F@039-SN1MPN1-003.039d.mgd.msft.net> <1322122592.24797.299.camel@sauron.fi.intel.com> In-Reply-To: <1322122592.24797.299.camel@sauron.fi.intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: quoted-printable Cc: "Artem.Bityutskiy@nokia.com" , Li Yang-R58472 , Wood Scott-B07421 , "dwmw2@infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "akpm@linux-foundation.org" , "linuxppc-dev@lists.ozlabs.org" List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , =E4=BA=8E 2011=E5=B9=B411=E6=9C=8824=E6=97=A5 16:16, Artem Bityutskiy =E5= =86=99=E9=81=93: > On Thu, 2011-11-24 at 07:49 +0000, Li Yang-R58472 wrote: >>> Subject: Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to s= upport >>> large-page Nand chip >>> >>> On Thu, 2011-11-24 at 08:41 +0800, b35362@freescale.com wrote: >>>> + /* >>>> + * Freescale FCM controller has a 2K size limitation= of buffer >>>> + * RAM, so elbc_fcm_ctrl->buffer have to be used if = writesize >>>> + * of chip is greater than 2048. >>>> + * We malloc a large enough buffer (maximum page siz= e is >>> 16K). >>>> + */ >>>> + elbc_fcm_ctrl->buffer =3D kmalloc(1024 * 16 + 1024, >>> GFP_KERNEL); >>> >>> Are there NANDs with 16KiB page size? >> We are not sure, but are there possibility that chip with 16K page wil= l appear? Or maybe we can add a MACRO for the maximum page size? > I do not know, but I know that allocating 32KiB of contiguous physical > RAM may cause unneeded memory pressure and even fail if the memory is > too fragmented. So I would not go for this unless this is necessary. What is your suggestion ? 8k is enough ? > Did you try to look how the NAND base interface could be changed to > avoid re-allocation altogether, BTW? This buffer is a controller-wide resource( as Scott said), I only=20 allocate buffer one time in this version. It should be a large enough buffer for all chips. -Liu Shuo From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe004.messaging.microsoft.com [216.32.181.184]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 872B81007DB for ; Thu, 24 Nov 2011 20:59:03 +1100 (EST) Message-ID: <4ECE162D.7080408@freescale.com> Date: Thu, 24 Nov 2011 18:02:21 +0800 From: LiuShuo MIME-Version: 1.0 To: Subject: Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to support large-page Nand chip References: <1322095306-13156-1-git-send-email-b35362@freescale.com> <1322095306-13156-3-git-send-email-b35362@freescale.com> <1322120515.24797.296.camel@sauron.fi.intel.com> <3F607A5180246847A760FD34122A1E052DC61F@039-SN1MPN1-003.039d.mgd.msft.net> <1322122592.24797.299.camel@sauron.fi.intel.com> In-Reply-To: <1322122592.24797.299.camel@sauron.fi.intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Cc: "Artem.Bityutskiy@nokia.com" , Li Yang-R58472 , Wood Scott-B07421 , "dwmw2@infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "akpm@linux-foundation.org" , "linuxppc-dev@lists.ozlabs.org" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , =E4=BA=8E 2011=E5=B9=B411=E6=9C=8824=E6=97=A5 16:16, Artem Bityutskiy =E5= =86=99=E9=81=93: > On Thu, 2011-11-24 at 07:49 +0000, Li Yang-R58472 wrote: >>> Subject: Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to s= upport >>> large-page Nand chip >>> >>> On Thu, 2011-11-24 at 08:41 +0800, b35362@freescale.com wrote: >>>> + /* >>>> + * Freescale FCM controller has a 2K size limitation= of buffer >>>> + * RAM, so elbc_fcm_ctrl->buffer have to be used if = writesize >>>> + * of chip is greater than 2048. >>>> + * We malloc a large enough buffer (maximum page siz= e is >>> 16K). >>>> + */ >>>> + elbc_fcm_ctrl->buffer =3D kmalloc(1024 * 16 + 1024, >>> GFP_KERNEL); >>> >>> Are there NANDs with 16KiB page size? >> We are not sure, but are there possibility that chip with 16K page wil= l appear? Or maybe we can add a MACRO for the maximum page size? > I do not know, but I know that allocating 32KiB of contiguous physical > RAM may cause unneeded memory pressure and even fail if the memory is > too fragmented. So I would not go for this unless this is necessary. What is your suggestion ? 8k is enough ? > Did you try to look how the NAND base interface could be changed to > avoid re-allocation altogether, BTW? This buffer is a controller-wide resource( as Scott said), I only=20 allocate buffer one time in this version. It should be a large enough buffer for all chips. -Liu Shuo From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755358Ab1KXJ66 (ORCPT ); Thu, 24 Nov 2011 04:58:58 -0500 Received: from ch1ehsobe003.messaging.microsoft.com ([216.32.181.183]:37579 "EHLO ch1outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754941Ab1KXJ64 convert rfc822-to-8bit (ORCPT ); Thu, 24 Nov 2011 04:58:56 -0500 X-SpamScore: -12 X-BigFish: VS-12(zzc89bh936eK1432N98dKzz1202hzz8275bhz2dh2a8h668h839h93fh) X-Forefront-Antispam-Report: CIP:70.37.183.190;KIP:(null);UIP:(null);IPV:NLI;H:mail.freescale.net;RD:none;EFVD:NLI X-FB-SS: 13, Message-ID: <4ECE162D.7080408@freescale.com> Date: Thu, 24 Nov 2011 18:02:21 +0800 From: LiuShuo User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.14) Gecko/20110223 Thunderbird/3.1.8 MIME-Version: 1.0 To: CC: Li Yang-R58472 , "dwmw2@infradead.org" , "Artem.Bityutskiy@nokia.com" , Wood Scott-B07421 , "linux-mtd@lists.infradead.org" , "linuxppc-dev@lists.ozlabs.org" , "akpm@linux-foundation.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to support large-page Nand chip References: <1322095306-13156-1-git-send-email-b35362@freescale.com> <1322095306-13156-3-git-send-email-b35362@freescale.com> <1322120515.24797.296.camel@sauron.fi.intel.com> <3F607A5180246847A760FD34122A1E052DC61F@039-SN1MPN1-003.039d.mgd.msft.net> <1322122592.24797.299.camel@sauron.fi.intel.com> In-Reply-To: <1322122592.24797.299.camel@sauron.fi.intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8BIT X-OriginatorOrg: freescale.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 于 2011年11月24日 16:16, Artem Bityutskiy 写道: > On Thu, 2011-11-24 at 07:49 +0000, Li Yang-R58472 wrote: >>> Subject: Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to support >>> large-page Nand chip >>> >>> On Thu, 2011-11-24 at 08:41 +0800, b35362@freescale.com wrote: >>>> + /* >>>> + * Freescale FCM controller has a 2K size limitation of buffer >>>> + * RAM, so elbc_fcm_ctrl->buffer have to be used if writesize >>>> + * of chip is greater than 2048. >>>> + * We malloc a large enough buffer (maximum page size is >>> 16K). >>>> + */ >>>> + elbc_fcm_ctrl->buffer = kmalloc(1024 * 16 + 1024, >>> GFP_KERNEL); >>> >>> Are there NANDs with 16KiB page size? >> We are not sure, but are there possibility that chip with 16K page will appear? Or maybe we can add a MACRO for the maximum page size? > I do not know, but I know that allocating 32KiB of contiguous physical > RAM may cause unneeded memory pressure and even fail if the memory is > too fragmented. So I would not go for this unless this is necessary. What is your suggestion ? 8k is enough ? > Did you try to look how the NAND base interface could be changed to > avoid re-allocation altogether, BTW? This buffer is a controller-wide resource( as Scott said), I only allocate buffer one time in this version. It should be a large enough buffer for all chips. -Liu Shuo