From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:56147) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RVikv-0000mE-7t for qemu-devel@nongnu.org; Wed, 30 Nov 2011 06:55:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RViku-0001ze-4X for qemu-devel@nongnu.org; Wed, 30 Nov 2011 06:55:17 -0500 Received: from mout.web.de ([212.227.15.3]:62086) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RVikt-0001zW-Lz for qemu-devel@nongnu.org; Wed, 30 Nov 2011 06:55:16 -0500 Message-ID: <4ED61970.9040303@web.de> Date: Wed, 30 Nov 2011 12:54:24 +0100 From: =?ISO-8859-1?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1319278273-32437-1-git-send-email-khansa@kics.edu.pk> <1319278273-32437-6-git-send-email-khansa@kics.edu.pk> <4EA2AACE.3040602@web.de> <4EAF03E5.6020508@web.de> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v3 5/6] target-mips: Adding support for Cavium specific instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Khansa Butt Cc: qemu-devel@nongnu.org, Aurelien Jarno , Richard Henderson Am 22.11.2011 09:31, schrieb Khansa Butt: > On Tue, Nov 1, 2011 at 1:24 AM, Andreas Färber wrote: >> >> Am 28.10.2011 06:42, schrieb Khansa Butt: >>> >>> >>> On Sat, Oct 22, 2011 at 4:36 PM, Andreas Färber >> > wrote: >>> >>> Am 22.10.2011 12:11, schrieb khansa@kics.edu.pk >>> : >>> >>> > diff --git a/target-mips/machine.c b/target-mips/machine.c >>> > index be72b36..a274ce2 100644 >>> > --- a/target-mips/machine.c >>> > +++ b/target-mips/machine.c >>> > @@ -173,6 +179,12 @@ static void load_tc(QEMUFile *f, TCState *tc) >>> > qemu_get_betls(f, &tc->CP0_TCSchedule); >>> > qemu_get_betls(f, &tc->CP0_TCScheFBack); >>> > qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus); >>> > + qemu_get_betls(f, &tc->MPL0); >>> > + qemu_get_betls(f, &tc->MPL1); >>> > + qemu_get_betls(f, &tc->MPL2); >>> > + qemu_get_betls(f, &tc->P0); >>> > + qemu_get_betls(f, &tc->P1); >>> > + qemu_get_betls(f, &tc->P2); >>> > } >>> > >>> > static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) >>> >>> You're saving new fields, so you'll need to bump the version somewhere. >>> For loading, since you're adding at the end, you might be able to make >>> your additions conditional on the to-be-bumped version. >>> >>> >>> I 'm not able to understand " bump the version somewhere" kindly >>> explain this. >> >> "Somewhere" indicates I don't know the exact line for mips. Compare the >> recent patch to arm_gic. >> The general idea is that QEMU needs to be able to load files saved with >> an older version, the file format is therefore versioned. If you >> unconditionally try to load your new registers, you break loading older >> files that don't include them. > > Thanks for your response. > As I can't see any example of bumping the version of registers in > mips ( 32 or 64) so i'm in a bit difficult situation > From arm_gic what i understand is that version_id is related to > devices which are specific to some board > as gic is related to RealView board. considering that i'm in user > mode, can i do the same thing with Cavium's registers as these are > related to multiplier unit? No, this is not board- or device-specific, it's CPU-specific. Cf. target-mips/cpu.h:CPU_SAVE_VERSION target-mips/savevm.c:cpu_load() My suggestion was to bump CPU_SAVE_VERSION to 4, change the error check to "if (version_id < 3)" and to enclose your cpuo_load() additions in "if (version_id >= 4) { ... }". Depending how long you need to resend, note that Juan is working on a VMState refactoring of machine.c, which will make it more like devices. Andreas