* [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller @ 2011-12-06 8:54 Shengzhou Liu 2011-12-06 8:54 ` [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL " Shengzhou Liu 2011-12-06 17:16 ` [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale " Scott Wood 0 siblings, 2 replies; 15+ messages in thread From: Shengzhou Liu @ 2011-12-06 8:54 UTC (permalink / raw) To: linuxppc-dev; +Cc: scottwood, dwmw2, kumar.gala, linux-mtd, Shengzhou Liu There was a bug for fmr initialization, which lead to fmr was always 0x100 in fsl_elbc_chip_init() and caused FCM command timeout before calling fsl_elbc_chip_init_tail(), now we initialize CWTO to maximum timeout value and not relying on the setting of bootloader. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> --- v2: make fmr not relying on the setting of bootloader. drivers/mtd/nand/fsl_elbc_nand.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index eedd8ee..4f405a0 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -659,9 +659,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) if (chip->pagemask & 0xff000000) al++; - /* add to ECCM mode set in fsl_elbc_init */ - priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */ - (al << FMR_AL_SHIFT); + priv->fmr |= al << FMR_AL_SHIFT; dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", chip->numchips); @@ -764,8 +762,10 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) priv->mtd.priv = chip; priv->mtd.owner = THIS_MODULE; - /* Set the ECCM according to the settings in bootloader.*/ - priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM; + /* set timeout to maximum */ + priv->fmr = 15 << FMR_CWTO_SHIFT; + if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) + priv->fmr |= FMR_ECCM; /* fill in nand_chip structure */ /* set up function call table */ -- 1.6.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller 2011-12-06 8:54 [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller Shengzhou Liu @ 2011-12-06 8:54 ` Shengzhou Liu 2011-12-06 17:17 ` Scott Wood 2011-12-06 17:16 ` [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale " Scott Wood 1 sibling, 1 reply; 15+ messages in thread From: Shengzhou Liu @ 2011-12-06 8:54 UTC (permalink / raw) To: linuxppc-dev; +Cc: scottwood, dwmw2, kumar.gala, linux-mtd, Shengzhou Liu - fix NAND_CMD_READID command for ONFI detect. - add NAND_CMD_PARAM command to read the ONFI parameter page. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> --- v2: no changes drivers/mtd/nand/fsl_elbc_nand.c | 19 ++++++++++++------- 1 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 4f405a0..b4db407 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -349,19 +349,24 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, fsl_elbc_run_command(mtd); return; - /* READID must read all 5 possible bytes while CEB is active */ case NAND_CMD_READID: - dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n"); + case NAND_CMD_PARAM: + dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command); out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) | (FIR_OP_UA << FIR_OP1_SHIFT) | (FIR_OP_RBW << FIR_OP2_SHIFT)); - out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT); - /* nand_get_flash_type() reads 8 bytes of entire ID string */ - out_be32(&lbc->fbcr, 8); - elbc_fcm_ctrl->read_bytes = 8; + out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); + /* reads 8 bytes of entire ID string */ + if (NAND_CMD_READID == command) { + out_be32(&lbc->fbcr, 8); + elbc_fcm_ctrl->read_bytes = 8; + } else { + out_be32(&lbc->fbcr, 256); + elbc_fcm_ctrl->read_bytes = 256; + } elbc_fcm_ctrl->use_mdr = 1; - elbc_fcm_ctrl->mdr = 0; + elbc_fcm_ctrl->mdr = column; set_addr(mtd, 0, 0, 0); fsl_elbc_run_command(mtd); -- 1.6.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller 2011-12-06 8:54 ` [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL " Shengzhou Liu @ 2011-12-06 17:17 ` Scott Wood 2011-12-07 3:16 ` Liu Shengzhou-B36685 0 siblings, 1 reply; 15+ messages in thread From: Scott Wood @ 2011-12-06 17:17 UTC (permalink / raw) To: Shengzhou Liu; +Cc: linux-mtd, kumar.gala, linuxppc-dev, dwmw2 On 12/06/2011 02:54 AM, Shengzhou Liu wrote: > diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c > index 4f405a0..b4db407 100644 > --- a/drivers/mtd/nand/fsl_elbc_nand.c > +++ b/drivers/mtd/nand/fsl_elbc_nand.c > @@ -349,19 +349,24 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, > fsl_elbc_run_command(mtd); > return; > > - /* READID must read all 5 possible bytes while CEB is active */ > case NAND_CMD_READID: > - dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n"); > + case NAND_CMD_PARAM: > + dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command); > > out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) | > (FIR_OP_UA << FIR_OP1_SHIFT) | > (FIR_OP_RBW << FIR_OP2_SHIFT)); > - out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT); > - /* nand_get_flash_type() reads 8 bytes of entire ID string */ > - out_be32(&lbc->fbcr, 8); > - elbc_fcm_ctrl->read_bytes = 8; > + out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); > + /* reads 8 bytes of entire ID string */ > + if (NAND_CMD_READID == command) { if (command == NAND_CMD_READID) { > + out_be32(&lbc->fbcr, 8); > + elbc_fcm_ctrl->read_bytes = 8; > + } else { > + out_be32(&lbc->fbcr, 256); > + elbc_fcm_ctrl->read_bytes = 256; > + } Any harm in always using 256? -Scott ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller 2011-12-06 17:17 ` Scott Wood @ 2011-12-07 3:16 ` Liu Shengzhou-B36685 0 siblings, 0 replies; 15+ messages in thread From: Liu Shengzhou-B36685 @ 2011-12-07 3:16 UTC (permalink / raw) To: Wood Scott-B07421 Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780, linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org > -----Original Message----- > From: Wood Scott-B07421 > Sent: Wednesday, December 07, 2011 1:17 AM > To: Liu Shengzhou-B36685 > Cc: linuxppc-dev@lists.ozlabs.org; linux-mtd@lists.infradead.org; > dwmw2@infradead.org; Gala Kumar-B11780 > Subject: Re: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND > controller > > On 12/06/2011 02:54 AM, Shengzhou Liu wrote: > > diff --git a/drivers/mtd/nand/fsl_elbc_nand.c > b/drivers/mtd/nand/fsl_elbc_nand.c > > index 4f405a0..b4db407 100644 > > --- a/drivers/mtd/nand/fsl_elbc_nand.c > > +++ b/drivers/mtd/nand/fsl_elbc_nand.c > > @@ -349,19 +349,24 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, > unsigned int command, > > fsl_elbc_run_command(mtd); > > return; > > > > - /* READID must read all 5 possible bytes while CEB is active */ > > case NAND_CMD_READID: > > - dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n"); > > + case NAND_CMD_PARAM: > > + dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", > command); > > > > out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) | > > (FIR_OP_UA << FIR_OP1_SHIFT) | > > (FIR_OP_RBW << FIR_OP2_SHIFT)); > > - out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT); > > - /* nand_get_flash_type() reads 8 bytes of entire ID string */ > > - out_be32(&lbc->fbcr, 8); > > - elbc_fcm_ctrl->read_bytes = 8; > > + out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); > > + /* reads 8 bytes of entire ID string */ > > + if (NAND_CMD_READID == command) { > > if (command == NAND_CMD_READID) { > > > + out_be32(&lbc->fbcr, 8); > > + elbc_fcm_ctrl->read_bytes = 8; > > + } else { > > + out_be32(&lbc->fbcr, 256); > > + elbc_fcm_ctrl->read_bytes = 256; > > + } > > Any harm in always using 256? > > -Scott [Shengzhou] For NAND_CMD_READID command, the total bytes of entire ID string are 8, there are not 256 bytes so many, it's unnecessary and looks not so well logically to always using 256, though it works. ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller @ 2011-12-07 3:16 ` Liu Shengzhou-B36685 0 siblings, 0 replies; 15+ messages in thread From: Liu Shengzhou-B36685 @ 2011-12-07 3:16 UTC (permalink / raw) To: Wood Scott-B07421 Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780, linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org DQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIx DQo+IFNlbnQ6IFdlZG5lc2RheSwgRGVjZW1iZXIgMDcsIDIwMTEgMToxNyBBTQ0KPiBUbzogTGl1 IFNoZW5nemhvdS1CMzY2ODUNCj4gQ2M6IGxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMub3JnOyBs aW51eC1tdGRAbGlzdHMuaW5mcmFkZWFkLm9yZzsNCj4gZHdtdzJAaW5mcmFkZWFkLm9yZzsgR2Fs YSBLdW1hci1CMTE3ODANCj4gU3ViamVjdDogUmU6IFtQQVRDSCAyLzIgdjJdIG10ZC9uYW5kOiBB ZGQgT05GSSBzdXBwb3J0IGZvciBGU0wgTkFORA0KPiBjb250cm9sbGVyDQo+IA0KPiBPbiAxMi8w Ni8yMDExIDAyOjU0IEFNLCBTaGVuZ3pob3UgTGl1IHdyb3RlOg0KPiA+IGRpZmYgLS1naXQgYS9k cml2ZXJzL210ZC9uYW5kL2ZzbF9lbGJjX25hbmQuYw0KPiBiL2RyaXZlcnMvbXRkL25hbmQvZnNs X2VsYmNfbmFuZC5jDQo+ID4gaW5kZXggNGY0MDVhMC4uYjRkYjQwNyAxMDA2NDQNCj4gPiAtLS0g YS9kcml2ZXJzL210ZC9uYW5kL2ZzbF9lbGJjX25hbmQuYw0KPiA+ICsrKyBiL2RyaXZlcnMvbXRk L25hbmQvZnNsX2VsYmNfbmFuZC5jDQo+ID4gQEAgLTM0OSwxOSArMzQ5LDI0IEBAIHN0YXRpYyB2 b2lkIGZzbF9lbGJjX2NtZGZ1bmMoc3RydWN0IG10ZF9pbmZvICptdGQsDQo+IHVuc2lnbmVkIGlu dCBjb21tYW5kLA0KPiA+ICAJCWZzbF9lbGJjX3J1bl9jb21tYW5kKG10ZCk7DQo+ID4gIAkJcmV0 dXJuOw0KPiA+DQo+ID4gLQkvKiBSRUFESUQgbXVzdCByZWFkIGFsbCA1IHBvc3NpYmxlIGJ5dGVz IHdoaWxlIENFQiBpcyBhY3RpdmUgKi8NCj4gPiAgCWNhc2UgTkFORF9DTURfUkVBRElEOg0KPiA+ IC0JCWRldl92ZGJnKHByaXYtPmRldiwgImZzbF9lbGJjX2NtZGZ1bmM6IE5BTkRfQ01EX1JFQURJ RC5cbiIpOw0KPiA+ICsJY2FzZSBOQU5EX0NNRF9QQVJBTToNCj4gPiArCQlkZXZfdmRiZyhwcml2 LT5kZXYsICJmc2xfZWxiY19jbWRmdW5jOiBOQU5EX0NNRCAleFxuIiwNCj4gY29tbWFuZCk7DQo+ ID4NCj4gPiAgCQlvdXRfYmUzMigmbGJjLT5maXIsIChGSVJfT1BfQ00wIDw8IEZJUl9PUDBfU0hJ RlQpIHwNCj4gPiAgCQkgICAgICAgICAgICAgICAgICAgIChGSVJfT1BfVUEgIDw8IEZJUl9PUDFf U0hJRlQpIHwNCj4gPiAgCQkgICAgICAgICAgICAgICAgICAgIChGSVJfT1BfUkJXIDw8IEZJUl9P UDJfU0hJRlQpKTsNCj4gPiAtCQlvdXRfYmUzMigmbGJjLT5mY3IsIE5BTkRfQ01EX1JFQURJRCA8 PCBGQ1JfQ01EMF9TSElGVCk7DQo+ID4gLQkJLyogbmFuZF9nZXRfZmxhc2hfdHlwZSgpIHJlYWRz IDggYnl0ZXMgb2YgZW50aXJlIElEIHN0cmluZyAqLw0KPiA+IC0JCW91dF9iZTMyKCZsYmMtPmZi Y3IsIDgpOw0KPiA+IC0JCWVsYmNfZmNtX2N0cmwtPnJlYWRfYnl0ZXMgPSA4Ow0KPiA+ICsJCW91 dF9iZTMyKCZsYmMtPmZjciwgY29tbWFuZCA8PCBGQ1JfQ01EMF9TSElGVCk7DQo+ID4gKwkJLyog cmVhZHMgOCBieXRlcyBvZiBlbnRpcmUgSUQgc3RyaW5nICovDQo+ID4gKwkJaWYgKE5BTkRfQ01E X1JFQURJRCA9PSBjb21tYW5kKSB7DQo+IA0KPiBpZiAoY29tbWFuZCA9PSBOQU5EX0NNRF9SRUFE SUQpIHsNCj4gDQo+ID4gKwkJCW91dF9iZTMyKCZsYmMtPmZiY3IsIDgpOw0KPiA+ICsJCQllbGJj X2ZjbV9jdHJsLT5yZWFkX2J5dGVzID0gODsNCj4gPiArCQl9IGVsc2Ugew0KPiA+ICsJCQlvdXRf YmUzMigmbGJjLT5mYmNyLCAyNTYpOw0KPiA+ICsJCQllbGJjX2ZjbV9jdHJsLT5yZWFkX2J5dGVz ID0gMjU2Ow0KPiA+ICsJCX0NCj4gDQo+IEFueSBoYXJtIGluIGFsd2F5cyB1c2luZyAyNTY/DQo+ IA0KPiAtU2NvdHQNCltTaGVuZ3pob3VdIEZvciBOQU5EX0NNRF9SRUFESUQgY29tbWFuZCwgdGhl IHRvdGFsIGJ5dGVzIG9mIGVudGlyZSBJRCBzdHJpbmcgYXJlIDgsIHRoZXJlIGFyZSBub3QgMjU2 IGJ5dGVzIHNvIG1hbnksIGl0J3MgdW5uZWNlc3NhcnkgYW5kIGxvb2tzIG5vdCBzbyB3ZWxsIGxv Z2ljYWxseSB0byBhbHdheXMgdXNpbmcgMjU2LCB0aG91Z2ggaXQgd29ya3MuDQoNCg0K ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller 2011-12-07 3:16 ` Liu Shengzhou-B36685 (?) @ 2011-12-07 17:16 ` Scott Wood 2011-12-08 3:06 ` Liu Shengzhou-B36685 -1 siblings, 1 reply; 15+ messages in thread From: Scott Wood @ 2011-12-07 17:16 UTC (permalink / raw) To: Liu Shengzhou-B36685 Cc: Wood Scott-B07421, Gala Kumar-B11780, linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org, linux-mtd@lists.infradead.org On 12/06/2011 09:16 PM, Liu Shengzhou-B36685 wrote: >>> + out_be32(&lbc->fbcr, 8); >>> + elbc_fcm_ctrl->read_bytes = 8; >>> + } else { >>> + out_be32(&lbc->fbcr, 256); >>> + elbc_fcm_ctrl->read_bytes = 256; >>> + } >> >> Any harm in always using 256? >> >> -Scott > [Shengzhou] For NAND_CMD_READID command, the total bytes of entire ID string are 8, there are not 256 bytes so many, it's unnecessary and looks not so well logically to always using 256, though it works. It's not performance critical, and always using 256 keeps things simpler, and more robust if the length of the ID string grows in the future (we used to assume it was 5 bytes...). -Scott ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller 2011-12-07 17:16 ` Scott Wood @ 2011-12-08 3:06 ` Liu Shengzhou-B36685 0 siblings, 0 replies; 15+ messages in thread From: Liu Shengzhou-B36685 @ 2011-12-08 3:06 UTC (permalink / raw) To: Wood Scott-B07421 Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780, linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org Best Regards, Shengzhou Liu > -----Original Message----- > From: Wood Scott-B07421 > Sent: Thursday, December 08, 2011 1:16 AM > To: Liu Shengzhou-B36685 > Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; linux- > mtd@lists.infradead.org; dwmw2@infradead.org; Gala Kumar-B11780 > Subject: Re: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND > controller > > On 12/06/2011 09:16 PM, Liu Shengzhou-B36685 wrote: > >>> + out_be32(&lbc->fbcr, 8); > >>> + elbc_fcm_ctrl->read_bytes = 8; > >>> + } else { > >>> + out_be32(&lbc->fbcr, 256); > >>> + elbc_fcm_ctrl->read_bytes = 256; > >>> + } > >> > >> Any harm in always using 256? > >> > >> -Scott > > [Shengzhou] For NAND_CMD_READID command, the total bytes of entire ID > string are 8, there are not 256 bytes so many, it's unnecessary and looks > not so well logically to always using 256, though it works. > > It's not performance critical, and always using 256 keeps things simpler, > and more robust if the length of the ID string grows in the future (we > used to assume it was 5 bytes...). > > -Scott [Shengzhou] OK. ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller @ 2011-12-08 3:06 ` Liu Shengzhou-B36685 0 siblings, 0 replies; 15+ messages in thread From: Liu Shengzhou-B36685 @ 2011-12-08 3:06 UTC (permalink / raw) To: Wood Scott-B07421 Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780, linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org DQoNCkJlc3QgUmVnYXJkcywNClNoZW5nemhvdSBMaXUNCg0KDQo+IC0tLS0tT3JpZ2luYWwgTWVz c2FnZS0tLS0tDQo+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIxDQo+IFNlbnQ6IFRodXJzZGF5LCBE ZWNlbWJlciAwOCwgMjAxMSAxOjE2IEFNDQo+IFRvOiBMaXUgU2hlbmd6aG91LUIzNjY4NQ0KPiBD YzogV29vZCBTY290dC1CMDc0MjE7IGxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMub3JnOyBsaW51 eC0NCj4gbXRkQGxpc3RzLmluZnJhZGVhZC5vcmc7IGR3bXcyQGluZnJhZGVhZC5vcmc7IEdhbGEg S3VtYXItQjExNzgwDQo+IFN1YmplY3Q6IFJlOiBbUEFUQ0ggMi8yIHYyXSBtdGQvbmFuZDogQWRk IE9ORkkgc3VwcG9ydCBmb3IgRlNMIE5BTkQNCj4gY29udHJvbGxlcg0KPiANCj4gT24gMTIvMDYv MjAxMSAwOToxNiBQTSwgTGl1IFNoZW5nemhvdS1CMzY2ODUgd3JvdGU6DQo+ID4+PiArCQkJb3V0 X2JlMzIoJmxiYy0+ZmJjciwgOCk7DQo+ID4+PiArCQkJZWxiY19mY21fY3RybC0+cmVhZF9ieXRl cyA9IDg7DQo+ID4+PiArCQl9IGVsc2Ugew0KPiA+Pj4gKwkJCW91dF9iZTMyKCZsYmMtPmZiY3Is IDI1Nik7DQo+ID4+PiArCQkJZWxiY19mY21fY3RybC0+cmVhZF9ieXRlcyA9IDI1NjsNCj4gPj4+ ICsJCX0NCj4gPj4NCj4gPj4gQW55IGhhcm0gaW4gYWx3YXlzIHVzaW5nIDI1Nj8NCj4gPj4NCj4g Pj4gLVNjb3R0DQo+ID4gW1NoZW5nemhvdV0gRm9yIE5BTkRfQ01EX1JFQURJRCBjb21tYW5kLCB0 aGUgdG90YWwgYnl0ZXMgb2YgZW50aXJlIElEDQo+IHN0cmluZyBhcmUgOCwgdGhlcmUgYXJlIG5v dCAyNTYgYnl0ZXMgc28gbWFueSwgaXQncyB1bm5lY2Vzc2FyeSBhbmQgbG9va3MNCj4gbm90IHNv IHdlbGwgbG9naWNhbGx5IHRvIGFsd2F5cyB1c2luZyAyNTYsIHRob3VnaCBpdCB3b3Jrcy4NCj4g DQo+IEl0J3Mgbm90IHBlcmZvcm1hbmNlIGNyaXRpY2FsLCBhbmQgYWx3YXlzIHVzaW5nIDI1NiBr ZWVwcyB0aGluZ3Mgc2ltcGxlciwNCj4gYW5kIG1vcmUgcm9idXN0IGlmIHRoZSBsZW5ndGggb2Yg dGhlIElEIHN0cmluZyBncm93cyBpbiB0aGUgZnV0dXJlICh3ZQ0KPiB1c2VkIHRvIGFzc3VtZSBp dCB3YXMgNSBieXRlcy4uLikuDQo+IA0KPiAtU2NvdHQNCltTaGVuZ3pob3VdIE9LLg0K ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller 2011-12-06 8:54 [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller Shengzhou Liu 2011-12-06 8:54 ` [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL " Shengzhou Liu @ 2011-12-06 17:16 ` Scott Wood 2011-12-07 6:30 ` Liu Shengzhou-B36685 1 sibling, 1 reply; 15+ messages in thread From: Scott Wood @ 2011-12-06 17:16 UTC (permalink / raw) To: Shengzhou Liu; +Cc: linux-mtd, kumar.gala, linuxppc-dev, dwmw2 On 12/06/2011 02:54 AM, Shengzhou Liu wrote: > There was a bug for fmr initialization, which lead to fmr was always 0x100 > in fsl_elbc_chip_init() and caused FCM command timeout before calling > fsl_elbc_chip_init_tail(), now we initialize CWTO to maximum timeout value > and not relying on the setting of bootloader. > > Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> > --- > v2: make fmr not relying on the setting of bootloader. > > drivers/mtd/nand/fsl_elbc_nand.c | 10 +++++----- > 1 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c > index eedd8ee..4f405a0 100644 > --- a/drivers/mtd/nand/fsl_elbc_nand.c > +++ b/drivers/mtd/nand/fsl_elbc_nand.c > @@ -659,9 +659,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) > if (chip->pagemask & 0xff000000) > al++; > > - /* add to ECCM mode set in fsl_elbc_init */ > - priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */ > - (al << FMR_AL_SHIFT); > + priv->fmr |= al << FMR_AL_SHIFT; > > dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", > chip->numchips); > @@ -764,8 +762,10 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) > priv->mtd.priv = chip; > priv->mtd.owner = THIS_MODULE; > > - /* Set the ECCM according to the settings in bootloader.*/ > - priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM; > + /* set timeout to maximum */ > + priv->fmr = 15 << FMR_CWTO_SHIFT; > + if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) > + priv->fmr |= FMR_ECCM; Please do not change the way ECCM is handled. We probably should have done it this way from the start, but at this point it breaks compatibility if you have a large page flash and the firmware didn't touch NAND. -Scott ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller 2011-12-06 17:16 ` [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale " Scott Wood @ 2011-12-07 6:30 ` Liu Shengzhou-B36685 0 siblings, 0 replies; 15+ messages in thread From: Liu Shengzhou-B36685 @ 2011-12-07 6:30 UTC (permalink / raw) To: Wood Scott-B07421 Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780, linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org > -----Original Message----- > From: Wood Scott-B07421 > Sent: Wednesday, December 07, 2011 1:16 AM > To: Liu Shengzhou-B36685 > Cc: linuxppc-dev@lists.ozlabs.org; linux-mtd@lists.infradead.org; > dwmw2@infradead.org; Gala Kumar-B11780 > Subject: Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of > Freescale NAND controller > > On 12/06/2011 02:54 AM, Shengzhou Liu wrote: > > There was a bug for fmr initialization, which lead to fmr was always > > 0x100 in fsl_elbc_chip_init() and caused FCM command timeout before > > calling fsl_elbc_chip_init_tail(), now we initialize CWTO to maximum > > timeout value and not relying on the setting of bootloader. > > > > Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> > > --- > > v2: make fmr not relying on the setting of bootloader. > > > > drivers/mtd/nand/fsl_elbc_nand.c | 10 +++++----- > > 1 files changed, 5 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/mtd/nand/fsl_elbc_nand.c > > b/drivers/mtd/nand/fsl_elbc_nand.c > > index eedd8ee..4f405a0 100644 > > --- a/drivers/mtd/nand/fsl_elbc_nand.c > > +++ b/drivers/mtd/nand/fsl_elbc_nand.c > > @@ -659,9 +659,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info > *mtd) > > if (chip->pagemask & 0xff000000) > > al++; > > > > - /* add to ECCM mode set in fsl_elbc_init */ > > - priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */ > > - (al << FMR_AL_SHIFT); > > + priv->fmr |= al << FMR_AL_SHIFT; > > > > dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", > > chip->numchips); > > @@ -764,8 +762,10 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd > *priv) > > priv->mtd.priv = chip; > > priv->mtd.owner = THIS_MODULE; > > > > - /* Set the ECCM according to the settings in bootloader.*/ > > - priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM; > > + /* set timeout to maximum */ > > + priv->fmr = 15 << FMR_CWTO_SHIFT; > > + if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) > > + priv->fmr |= FMR_ECCM; > > Please do not change the way ECCM is handled. We probably should have > done it this way from the start, but at this point it breaks > compatibility if you have a large page flash and the firmware didn't > touch NAND. > > -Scott [Shengzhou] This patch doesn't change the way ECCM is handled, it's still same as before, just make sure CWTO timeout is set to maximum. ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller @ 2011-12-07 6:30 ` Liu Shengzhou-B36685 0 siblings, 0 replies; 15+ messages in thread From: Liu Shengzhou-B36685 @ 2011-12-07 6:30 UTC (permalink / raw) To: Wood Scott-B07421 Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780, linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org DQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIx DQo+IFNlbnQ6IFdlZG5lc2RheSwgRGVjZW1iZXIgMDcsIDIwMTEgMToxNiBBTQ0KPiBUbzogTGl1 IFNoZW5nemhvdS1CMzY2ODUNCj4gQ2M6IGxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMub3JnOyBs aW51eC1tdGRAbGlzdHMuaW5mcmFkZWFkLm9yZzsNCj4gZHdtdzJAaW5mcmFkZWFkLm9yZzsgR2Fs YSBLdW1hci1CMTE3ODANCj4gU3ViamVjdDogUmU6IFtQQVRDSCAxLzIgdjJdIG10ZC9uYW5kOiBm aXh1cCBmb3IgZm1yIGluaXRpYWxpemF0aW9uIG9mDQo+IEZyZWVzY2FsZSBOQU5EIGNvbnRyb2xs ZXINCj4gDQo+IE9uIDEyLzA2LzIwMTEgMDI6NTQgQU0sIFNoZW5nemhvdSBMaXUgd3JvdGU6DQo+ ID4gVGhlcmUgd2FzIGEgYnVnIGZvciBmbXIgaW5pdGlhbGl6YXRpb24sIHdoaWNoIGxlYWQgdG8g IGZtciB3YXMgYWx3YXlzDQo+ID4gMHgxMDAgaW4gZnNsX2VsYmNfY2hpcF9pbml0KCkgYW5kIGNh dXNlZCBGQ00gY29tbWFuZCB0aW1lb3V0IGJlZm9yZQ0KPiA+IGNhbGxpbmcgZnNsX2VsYmNfY2hp cF9pbml0X3RhaWwoKSwgbm93IHdlIGluaXRpYWxpemUgQ1dUTyB0byBtYXhpbXVtDQo+ID4gdGlt ZW91dCB2YWx1ZSBhbmQgbm90IHJlbHlpbmcgb24gdGhlIHNldHRpbmcgb2YgYm9vdGxvYWRlci4N Cj4gPg0KPiA+IFNpZ25lZC1vZmYtYnk6IFNoZW5nemhvdSBMaXUgPFNoZW5nemhvdS5MaXVAZnJl ZXNjYWxlLmNvbT4NCj4gPiAtLS0NCj4gPiB2MjogbWFrZSBmbXIgbm90IHJlbHlpbmcgb24gdGhl IHNldHRpbmcgb2YgYm9vdGxvYWRlci4NCj4gPg0KPiA+ICBkcml2ZXJzL210ZC9uYW5kL2ZzbF9l bGJjX25hbmQuYyB8ICAgMTAgKysrKystLS0tLQ0KPiA+ICAxIGZpbGVzIGNoYW5nZWQsIDUgaW5z ZXJ0aW9ucygrKSwgNSBkZWxldGlvbnMoLSkNCj4gPg0KPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJz L210ZC9uYW5kL2ZzbF9lbGJjX25hbmQuYw0KPiA+IGIvZHJpdmVycy9tdGQvbmFuZC9mc2xfZWxi Y19uYW5kLmMNCj4gPiBpbmRleCBlZWRkOGVlLi40ZjQwNWEwIDEwMDY0NA0KPiA+IC0tLSBhL2Ry aXZlcnMvbXRkL25hbmQvZnNsX2VsYmNfbmFuZC5jDQo+ID4gKysrIGIvZHJpdmVycy9tdGQvbmFu ZC9mc2xfZWxiY19uYW5kLmMNCj4gPiBAQCAtNjU5LDkgKzY1OSw3IEBAIHN0YXRpYyBpbnQgZnNs X2VsYmNfY2hpcF9pbml0X3RhaWwoc3RydWN0IG10ZF9pbmZvDQo+ICptdGQpDQo+ID4gIAlpZiAo Y2hpcC0+cGFnZW1hc2sgJiAweGZmMDAwMDAwKQ0KPiA+ICAJCWFsKys7DQo+ID4NCj4gPiAtCS8q IGFkZCB0byBFQ0NNIG1vZGUgc2V0IGluIGZzbF9lbGJjX2luaXQgKi8NCj4gPiAtCXByaXYtPmZt ciB8PSAoMTIgPDwgRk1SX0NXVE9fU0hJRlQpIHwgIC8qIFRpbWVvdXQgPiAxMiBtcyAqLw0KPiA+ IC0JICAgICAgICAgICAgIChhbCA8PCBGTVJfQUxfU0hJRlQpOw0KPiA+ICsJcHJpdi0+Zm1yIHw9 IGFsIDw8IEZNUl9BTF9TSElGVDsNCj4gPg0KPiA+ICAJZGV2X2RiZyhwcml2LT5kZXYsICJmc2xf ZWxiY19pbml0OiBuYW5kLT5udW1jaGlwcyA9ICVkXG4iLA0KPiA+ICAJICAgICAgICBjaGlwLT5u dW1jaGlwcyk7DQo+ID4gQEAgLTc2NCw4ICs3NjIsMTAgQEAgc3RhdGljIGludCBmc2xfZWxiY19j aGlwX2luaXQoc3RydWN0IGZzbF9lbGJjX210ZA0KPiAqcHJpdikNCj4gPiAgCXByaXYtPm10ZC5w cml2ID0gY2hpcDsNCj4gPiAgCXByaXYtPm10ZC5vd25lciA9IFRISVNfTU9EVUxFOw0KPiA+DQo+ ID4gLQkvKiBTZXQgdGhlIEVDQ00gYWNjb3JkaW5nIHRvIHRoZSBzZXR0aW5ncyBpbiBib290bG9h ZGVyLiovDQo+ID4gLQlwcml2LT5mbXIgPSBpbl9iZTMyKCZsYmMtPmZtcikgJiBGTVJfRUNDTTsN Cj4gPiArCS8qIHNldCB0aW1lb3V0IHRvIG1heGltdW0gKi8NCj4gPiArCXByaXYtPmZtciA9IDE1 IDw8IEZNUl9DV1RPX1NISUZUOw0KPiA+ICsJaWYgKGluX2JlMzIoJmxiYy0+YmFua1twcml2LT5i YW5rXS5vcikgJiBPUl9GQ01fUEdTKQ0KPiA+ICsJCXByaXYtPmZtciB8PSBGTVJfRUNDTTsNCj4g DQo+IFBsZWFzZSBkbyBub3QgY2hhbmdlIHRoZSB3YXkgRUNDTSBpcyBoYW5kbGVkLiAgV2UgcHJv YmFibHkgc2hvdWxkIGhhdmUNCj4gZG9uZSBpdCB0aGlzIHdheSBmcm9tIHRoZSBzdGFydCwgYnV0 IGF0IHRoaXMgcG9pbnQgaXQgYnJlYWtzDQo+IGNvbXBhdGliaWxpdHkgaWYgeW91IGhhdmUgYSBs YXJnZSBwYWdlIGZsYXNoIGFuZCB0aGUgZmlybXdhcmUgZGlkbid0DQo+IHRvdWNoIE5BTkQuDQo+ IA0KPiAtU2NvdHQNCltTaGVuZ3pob3VdIFRoaXMgcGF0Y2ggZG9lc24ndCBjaGFuZ2UgdGhlIHdh eSBFQ0NNIGlzIGhhbmRsZWQsIGl0J3Mgc3RpbGwgc2FtZSBhcyBiZWZvcmUsIGp1c3QgbWFrZSBz dXJlIENXVE8gdGltZW91dCBpcyBzZXQgdG8gbWF4aW11bS4gIA0K ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller 2011-12-07 6:30 ` Liu Shengzhou-B36685 (?) @ 2011-12-07 17:17 ` Scott Wood 2011-12-08 3:36 ` Liu Shengzhou-B36685 -1 siblings, 1 reply; 15+ messages in thread From: Scott Wood @ 2011-12-07 17:17 UTC (permalink / raw) To: Liu Shengzhou-B36685 Cc: Wood Scott-B07421, Gala Kumar-B11780, linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org, linux-mtd@lists.infradead.org On 12/07/2011 12:30 AM, Liu Shengzhou-B36685 wrote: > >> -----Original Message----- >> From: Wood Scott-B07421 >> Sent: Wednesday, December 07, 2011 1:16 AM >> To: Liu Shengzhou-B36685 >> Cc: linuxppc-dev@lists.ozlabs.org; linux-mtd@lists.infradead.org; >> dwmw2@infradead.org; Gala Kumar-B11780 >> Subject: Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of >> Freescale NAND controller >> >> On 12/06/2011 02:54 AM, Shengzhou Liu wrote: >>> There was a bug for fmr initialization, which lead to fmr was always >>> 0x100 in fsl_elbc_chip_init() and caused FCM command timeout before >>> calling fsl_elbc_chip_init_tail(), now we initialize CWTO to maximum >>> timeout value and not relying on the setting of bootloader. >>> >>> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> >>> --- >>> v2: make fmr not relying on the setting of bootloader. >>> >>> drivers/mtd/nand/fsl_elbc_nand.c | 10 +++++----- >>> 1 files changed, 5 insertions(+), 5 deletions(-) >>> >>> diff --git a/drivers/mtd/nand/fsl_elbc_nand.c >>> b/drivers/mtd/nand/fsl_elbc_nand.c >>> index eedd8ee..4f405a0 100644 >>> --- a/drivers/mtd/nand/fsl_elbc_nand.c >>> +++ b/drivers/mtd/nand/fsl_elbc_nand.c >>> @@ -659,9 +659,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info >> *mtd) >>> if (chip->pagemask & 0xff000000) >>> al++; >>> >>> - /* add to ECCM mode set in fsl_elbc_init */ >>> - priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */ >>> - (al << FMR_AL_SHIFT); >>> + priv->fmr |= al << FMR_AL_SHIFT; >>> >>> dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", >>> chip->numchips); >>> @@ -764,8 +762,10 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd >> *priv) >>> priv->mtd.priv = chip; >>> priv->mtd.owner = THIS_MODULE; >>> >>> - /* Set the ECCM according to the settings in bootloader.*/ >>> - priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM; >>> + /* set timeout to maximum */ >>> + priv->fmr = 15 << FMR_CWTO_SHIFT; >>> + if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) >>> + priv->fmr |= FMR_ECCM; >> >> Please do not change the way ECCM is handled. We probably should have >> done it this way from the start, but at this point it breaks >> compatibility if you have a large page flash and the firmware didn't >> touch NAND. >> >> -Scott > [Shengzhou] This patch doesn't change the way ECCM is handled, it's still same as before, just make sure CWTO timeout is set to maximum. It does change it. It used to use the existing value in FMR, and now it sets it based on ORn[PGS]. -Scott ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller 2011-12-07 17:17 ` Scott Wood @ 2011-12-08 3:36 ` Liu Shengzhou-B36685 0 siblings, 0 replies; 15+ messages in thread From: Liu Shengzhou-B36685 @ 2011-12-08 3:36 UTC (permalink / raw) To: Wood Scott-B07421 Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780, linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org > -----Original Message----- > From: Wood Scott-B07421 > Sent: Thursday, December 08, 2011 1:17 AM > To: Liu Shengzhou-B36685 > Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; linux- > mtd@lists.infradead.org; dwmw2@infradead.org; Gala Kumar-B11780 > Subject: Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of > Freescale NAND controller > > On 12/07/2011 12:30 AM, Liu Shengzhou-B36685 wrote: > > > >> -----Original Message----- > >> From: Wood Scott-B07421 > >> Sent: Wednesday, December 07, 2011 1:16 AM > >> To: Liu Shengzhou-B36685 > >> Cc: linuxppc-dev@lists.ozlabs.org; linux-mtd@lists.infradead.org; > >> dwmw2@infradead.org; Gala Kumar-B11780 > >> Subject: Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of > >> Freescale NAND controller > >> > >> On 12/06/2011 02:54 AM, Shengzhou Liu wrote: > >>> There was a bug for fmr initialization, which lead to fmr was > >>> always 0x100 in fsl_elbc_chip_init() and caused FCM command timeout > >>> before calling fsl_elbc_chip_init_tail(), now we initialize CWTO to > >>> maximum timeout value and not relying on the setting of bootloader. > >>> > >>> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> > >>> --- > >>> v2: make fmr not relying on the setting of bootloader. > >>> > >>> drivers/mtd/nand/fsl_elbc_nand.c | 10 +++++----- > >>> 1 files changed, 5 insertions(+), 5 deletions(-) > >>> > >>> diff --git a/drivers/mtd/nand/fsl_elbc_nand.c > >>> b/drivers/mtd/nand/fsl_elbc_nand.c > >>> index eedd8ee..4f405a0 100644 > >>> --- a/drivers/mtd/nand/fsl_elbc_nand.c > >>> +++ b/drivers/mtd/nand/fsl_elbc_nand.c > >>> @@ -659,9 +659,7 @@ static int fsl_elbc_chip_init_tail(struct > >>> mtd_info > >> *mtd) > >>> if (chip->pagemask & 0xff000000) > >>> al++; > >>> > >>> - /* add to ECCM mode set in fsl_elbc_init */ > >>> - priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */ > >>> - (al << FMR_AL_SHIFT); > >>> + priv->fmr |= al << FMR_AL_SHIFT; > >>> > >>> dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", > >>> chip->numchips); > >>> @@ -764,8 +762,10 @@ static int fsl_elbc_chip_init(struct > >>> fsl_elbc_mtd > >> *priv) > >>> priv->mtd.priv = chip; > >>> priv->mtd.owner = THIS_MODULE; > >>> > >>> - /* Set the ECCM according to the settings in bootloader.*/ > >>> - priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM; > >>> + /* set timeout to maximum */ > >>> + priv->fmr = 15 << FMR_CWTO_SHIFT; > >>> + if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) > >>> + priv->fmr |= FMR_ECCM; > >> > >> Please do not change the way ECCM is handled. We probably should > >> have done it this way from the start, but at this point it breaks > >> compatibility if you have a large page flash and the firmware didn't > >> touch NAND. > >> > >> -Scott > > [Shengzhou] This patch doesn't change the way ECCM is handled, it's > still same as before, just make sure CWTO timeout is set to maximum. > > It does change it. It used to use the existing value in FMR, and now it > sets it based on ORn[PGS]. > > -Scott [Shengzhou] In u-boot: #ifdef CONFIG_FSL_ELBC_FMR priv->fmr = CONFIG_FSL_ELBC_FMR; #else priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT); or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or); if (or & OR_FCM_PGS) priv->fmr |= FMR_ECCM; #endif In kernel: It used to be " priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM ", so fmr was always 0x100(or 0,depend on ORn[PGS]), CWTO was 0(timeout was minimum). In this patch, for not relying on bootloader, fmr is initialized as what u-boot does, except FMR_AL_SHIFT is handled in fsl_elbc_chip_init_tail and without definition of CONFIG_FSL_ELBC_FMR. So, it doesn't change it. Do we still need CONFIG_FSL_ELBC_FMR in kernel? ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller @ 2011-12-08 3:36 ` Liu Shengzhou-B36685 0 siblings, 0 replies; 15+ messages in thread From: Liu Shengzhou-B36685 @ 2011-12-08 3:36 UTC (permalink / raw) To: Wood Scott-B07421 Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780, linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBTY290dC1CMDc0 MjENCj4gU2VudDogVGh1cnNkYXksIERlY2VtYmVyIDA4LCAyMDExIDE6MTcgQU0NCj4gVG86IExp dSBTaGVuZ3pob3UtQjM2Njg1DQo+IENjOiBXb29kIFNjb3R0LUIwNzQyMTsgbGludXhwcGMtZGV2 QGxpc3RzLm96bGFicy5vcmc7IGxpbnV4LQ0KPiBtdGRAbGlzdHMuaW5mcmFkZWFkLm9yZzsgZHdt dzJAaW5mcmFkZWFkLm9yZzsgR2FsYSBLdW1hci1CMTE3ODANCj4gU3ViamVjdDogUmU6IFtQQVRD SCAxLzIgdjJdIG10ZC9uYW5kOiBmaXh1cCBmb3IgZm1yIGluaXRpYWxpemF0aW9uIG9mDQo+IEZy ZWVzY2FsZSBOQU5EIGNvbnRyb2xsZXINCj4gDQo+IE9uIDEyLzA3LzIwMTEgMTI6MzAgQU0sIExp dSBTaGVuZ3pob3UtQjM2Njg1IHdyb3RlOg0KPiA+DQo+ID4+IC0tLS0tT3JpZ2luYWwgTWVzc2Fn ZS0tLS0tDQo+ID4+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIxDQo+ID4+IFNlbnQ6IFdlZG5lc2Rh eSwgRGVjZW1iZXIgMDcsIDIwMTEgMToxNiBBTQ0KPiA+PiBUbzogTGl1IFNoZW5nemhvdS1CMzY2 ODUNCj4gPj4gQ2M6IGxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMub3JnOyBsaW51eC1tdGRAbGlz dHMuaW5mcmFkZWFkLm9yZzsNCj4gPj4gZHdtdzJAaW5mcmFkZWFkLm9yZzsgR2FsYSBLdW1hci1C MTE3ODANCj4gPj4gU3ViamVjdDogUmU6IFtQQVRDSCAxLzIgdjJdIG10ZC9uYW5kOiBmaXh1cCBm b3IgZm1yIGluaXRpYWxpemF0aW9uIG9mDQo+ID4+IEZyZWVzY2FsZSBOQU5EIGNvbnRyb2xsZXIN Cj4gPj4NCj4gPj4gT24gMTIvMDYvMjAxMSAwMjo1NCBBTSwgU2hlbmd6aG91IExpdSB3cm90ZToN Cj4gPj4+IFRoZXJlIHdhcyBhIGJ1ZyBmb3IgZm1yIGluaXRpYWxpemF0aW9uLCB3aGljaCBsZWFk IHRvICBmbXIgd2FzDQo+ID4+PiBhbHdheXMgMHgxMDAgaW4gZnNsX2VsYmNfY2hpcF9pbml0KCkg YW5kIGNhdXNlZCBGQ00gY29tbWFuZCB0aW1lb3V0DQo+ID4+PiBiZWZvcmUgY2FsbGluZyBmc2xf ZWxiY19jaGlwX2luaXRfdGFpbCgpLCBub3cgd2UgaW5pdGlhbGl6ZSBDV1RPIHRvDQo+ID4+PiBt YXhpbXVtIHRpbWVvdXQgdmFsdWUgYW5kIG5vdCByZWx5aW5nIG9uIHRoZSBzZXR0aW5nIG9mIGJv b3Rsb2FkZXIuDQo+ID4+Pg0KPiA+Pj4gU2lnbmVkLW9mZi1ieTogU2hlbmd6aG91IExpdSA8U2hl bmd6aG91LkxpdUBmcmVlc2NhbGUuY29tPg0KPiA+Pj4gLS0tDQo+ID4+PiB2MjogbWFrZSBmbXIg bm90IHJlbHlpbmcgb24gdGhlIHNldHRpbmcgb2YgYm9vdGxvYWRlci4NCj4gPj4+DQo+ID4+PiAg ZHJpdmVycy9tdGQvbmFuZC9mc2xfZWxiY19uYW5kLmMgfCAgIDEwICsrKysrLS0tLS0NCj4gPj4+ ICAxIGZpbGVzIGNoYW5nZWQsIDUgaW5zZXJ0aW9ucygrKSwgNSBkZWxldGlvbnMoLSkNCj4gPj4+ DQo+ID4+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9tdGQvbmFuZC9mc2xfZWxiY19uYW5kLmMNCj4g Pj4+IGIvZHJpdmVycy9tdGQvbmFuZC9mc2xfZWxiY19uYW5kLmMNCj4gPj4+IGluZGV4IGVlZGQ4 ZWUuLjRmNDA1YTAgMTAwNjQ0DQo+ID4+PiAtLS0gYS9kcml2ZXJzL210ZC9uYW5kL2ZzbF9lbGJj X25hbmQuYw0KPiA+Pj4gKysrIGIvZHJpdmVycy9tdGQvbmFuZC9mc2xfZWxiY19uYW5kLmMNCj4g Pj4+IEBAIC02NTksOSArNjU5LDcgQEAgc3RhdGljIGludCBmc2xfZWxiY19jaGlwX2luaXRfdGFp bChzdHJ1Y3QNCj4gPj4+IG10ZF9pbmZvDQo+ID4+ICptdGQpDQo+ID4+PiAgCWlmIChjaGlwLT5w YWdlbWFzayAmIDB4ZmYwMDAwMDApDQo+ID4+PiAgCQlhbCsrOw0KPiA+Pj4NCj4gPj4+IC0JLyog YWRkIHRvIEVDQ00gbW9kZSBzZXQgaW4gZnNsX2VsYmNfaW5pdCAqLw0KPiA+Pj4gLQlwcml2LT5m bXIgfD0gKDEyIDw8IEZNUl9DV1RPX1NISUZUKSB8ICAvKiBUaW1lb3V0ID4gMTIgbXMgKi8NCj4g Pj4+IC0JICAgICAgICAgICAgIChhbCA8PCBGTVJfQUxfU0hJRlQpOw0KPiA+Pj4gKwlwcml2LT5m bXIgfD0gYWwgPDwgRk1SX0FMX1NISUZUOw0KPiA+Pj4NCj4gPj4+ICAJZGV2X2RiZyhwcml2LT5k ZXYsICJmc2xfZWxiY19pbml0OiBuYW5kLT5udW1jaGlwcyA9ICVkXG4iLA0KPiA+Pj4gIAkgICAg ICAgIGNoaXAtPm51bWNoaXBzKTsNCj4gPj4+IEBAIC03NjQsOCArNzYyLDEwIEBAIHN0YXRpYyBp bnQgZnNsX2VsYmNfY2hpcF9pbml0KHN0cnVjdA0KPiA+Pj4gZnNsX2VsYmNfbXRkDQo+ID4+ICpw cml2KQ0KPiA+Pj4gIAlwcml2LT5tdGQucHJpdiA9IGNoaXA7DQo+ID4+PiAgCXByaXYtPm10ZC5v d25lciA9IFRISVNfTU9EVUxFOw0KPiA+Pj4NCj4gPj4+IC0JLyogU2V0IHRoZSBFQ0NNIGFjY29y ZGluZyB0byB0aGUgc2V0dGluZ3MgaW4gYm9vdGxvYWRlci4qLw0KPiA+Pj4gLQlwcml2LT5mbXIg PSBpbl9iZTMyKCZsYmMtPmZtcikgJiBGTVJfRUNDTTsNCj4gPj4+ICsJLyogc2V0IHRpbWVvdXQg dG8gbWF4aW11bSAqLw0KPiA+Pj4gKwlwcml2LT5mbXIgPSAxNSA8PCBGTVJfQ1dUT19TSElGVDsN Cj4gPj4+ICsJaWYgKGluX2JlMzIoJmxiYy0+YmFua1twcml2LT5iYW5rXS5vcikgJiBPUl9GQ01f UEdTKQ0KPiA+Pj4gKwkJcHJpdi0+Zm1yIHw9IEZNUl9FQ0NNOw0KPiA+Pg0KPiA+PiBQbGVhc2Ug ZG8gbm90IGNoYW5nZSB0aGUgd2F5IEVDQ00gaXMgaGFuZGxlZC4gIFdlIHByb2JhYmx5IHNob3Vs ZA0KPiA+PiBoYXZlIGRvbmUgaXQgdGhpcyB3YXkgZnJvbSB0aGUgc3RhcnQsIGJ1dCBhdCB0aGlz IHBvaW50IGl0IGJyZWFrcw0KPiA+PiBjb21wYXRpYmlsaXR5IGlmIHlvdSBoYXZlIGEgbGFyZ2Ug cGFnZSBmbGFzaCBhbmQgdGhlIGZpcm13YXJlIGRpZG4ndA0KPiA+PiB0b3VjaCBOQU5ELg0KPiA+ Pg0KPiA+PiAtU2NvdHQNCj4gPiBbU2hlbmd6aG91XSBUaGlzIHBhdGNoIGRvZXNuJ3QgY2hhbmdl IHRoZSB3YXkgRUNDTSBpcyBoYW5kbGVkLCBpdCdzDQo+IHN0aWxsIHNhbWUgYXMgYmVmb3JlLCBq dXN0IG1ha2Ugc3VyZSBDV1RPIHRpbWVvdXQgaXMgc2V0IHRvIG1heGltdW0uDQo+IA0KPiBJdCBk b2VzIGNoYW5nZSBpdC4gIEl0IHVzZWQgdG8gdXNlIHRoZSBleGlzdGluZyB2YWx1ZSBpbiBGTVIs IGFuZCBub3cgaXQNCj4gc2V0cyBpdCBiYXNlZCBvbiBPUm5bUEdTXS4NCj4gDQo+IC1TY290dA0K DQpbU2hlbmd6aG91XQ0KICBJbiB1LWJvb3Q6DQoJI2lmZGVmIENPTkZJR19GU0xfRUxCQ19GTVIN CiAgICAgICAgICAgcHJpdi0+Zm1yID0gQ09ORklHX0ZTTF9FTEJDX0ZNUjsNCgkjZWxzZQ0KCSAg ICAgcHJpdi0+Zm1yID0gKDE1IDw8IEZNUl9DV1RPX1NISUZUKSB8ICgyIDw8IEZNUl9BTF9TSElG VCk7DQoJICAgICBvciA9IGluX2JlMzIoJmVsYmNfY3RybC0+cmVncy0+YmFua1twcml2LT5iYW5r XS5vcik7DQoJICAgICBpZiAob3IgJiBPUl9GQ01fUEdTKQ0KICAgIAkJICAgICAgIHByaXYtPmZt ciB8PSBGTVJfRUNDTTsNCgkjZW5kaWYNCg0KICBJbiBrZXJuZWw6IEl0IHVzZWQgdG8gYmUgIiBw cml2LT5mbXIgPSBpbl9iZTMyKCZsYmMtPmZtcikgJiBGTVJfRUNDTSAiLCBzbyBmbXIgd2FzIGFs d2F5cyAweDEwMChvciAwLGRlcGVuZCBvbiBPUm5bUEdTXSksIENXVE8gd2FzIDAodGltZW91dCB3 YXMgbWluaW11bSkuICAgSW4gdGhpcyBwYXRjaCwgZm9yIG5vdCByZWx5aW5nIG9uIGJvb3Rsb2Fk ZXIsIGZtciBpcyBpbml0aWFsaXplZCBhcyB3aGF0IHUtYm9vdCBkb2VzLCBleGNlcHQgRk1SX0FM X1NISUZUIGlzIGhhbmRsZWQgaW4gZnNsX2VsYmNfY2hpcF9pbml0X3RhaWwgYW5kIHdpdGhvdXQg ZGVmaW5pdGlvbiBvZiBDT05GSUdfRlNMX0VMQkNfRk1SLg0KDQogIFNvLCBpdCBkb2Vzbid0IGNo YW5nZSBpdC4gRG8gd2Ugc3RpbGwgbmVlZCBDT05GSUdfRlNMX0VMQkNfRk1SIGluIGtlcm5lbD8g DQo= ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller 2011-12-08 3:36 ` Liu Shengzhou-B36685 (?) @ 2011-12-08 18:00 ` Scott Wood -1 siblings, 0 replies; 15+ messages in thread From: Scott Wood @ 2011-12-08 18:00 UTC (permalink / raw) To: Liu Shengzhou-B36685 Cc: Wood Scott-B07421, Gala Kumar-B11780, linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org, linux-mtd@lists.infradead.org On 12/07/2011 09:36 PM, Liu Shengzhou-B36685 wrote: > > >> -----Original Message----- >> From: Wood Scott-B07421 >> Sent: Thursday, December 08, 2011 1:17 AM >> To: Liu Shengzhou-B36685 >> Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; linux- >> mtd@lists.infradead.org; dwmw2@infradead.org; Gala Kumar-B11780 >> Subject: Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of >> Freescale NAND controller >> >> On 12/07/2011 12:30 AM, Liu Shengzhou-B36685 wrote: >>> [Shengzhou] This patch doesn't change the way ECCM is handled, it's >> still same as before, just make sure CWTO timeout is set to maximum. >> >> It does change it. It used to use the existing value in FMR, and now it >> sets it based on ORn[PGS]. >> >> -Scott > > [Shengzhou] > In u-boot: > #ifdef CONFIG_FSL_ELBC_FMR > priv->fmr = CONFIG_FSL_ELBC_FMR; > #else > priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT); > or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or); > if (or & OR_FCM_PGS) > priv->fmr |= FMR_ECCM; > #endif > > In kernel: It used to be " priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM > ", so fmr was always 0x100(or 0,depend on ORn[PGS]), CWTO was > 0(timeout was minimum). In this patch, for not relying on > bootloader, fmr is initialized as what u-boot does, except > FMR_AL_SHIFT is handled in fsl_elbc_chip_init_tail and without > definition of CONFIG_FSL_ELBC_FMR. > > So, it doesn't change it. You're assuming that the above U-Boot code is always run. This depends on whether the NAND driver is enabled in U-Boot. In the future, though, it might also depend on whether a NAND command is actually run in U-Boot -- this makes the setting of FMR non-deterministic between boots, which is worse than a one-time breakage of an unusual setup (driver not enabled in U-Boot at all). So it is a change, but I now think it's a change we should make. The changelog should mention that this is happening, though. > Do we still need CONFIG_FSL_ELBC_FMR in kernel? We do not want such a compile-time constant in the kernel. Use ORn[PGS] as the patch currently does. -Scott ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2011-12-08 18:00 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2011-12-06 8:54 [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller Shengzhou Liu 2011-12-06 8:54 ` [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL " Shengzhou Liu 2011-12-06 17:17 ` Scott Wood 2011-12-07 3:16 ` Liu Shengzhou-B36685 2011-12-07 3:16 ` Liu Shengzhou-B36685 2011-12-07 17:16 ` Scott Wood 2011-12-08 3:06 ` Liu Shengzhou-B36685 2011-12-08 3:06 ` Liu Shengzhou-B36685 2011-12-06 17:16 ` [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale " Scott Wood 2011-12-07 6:30 ` Liu Shengzhou-B36685 2011-12-07 6:30 ` Liu Shengzhou-B36685 2011-12-07 17:17 ` Scott Wood 2011-12-08 3:36 ` Liu Shengzhou-B36685 2011-12-08 3:36 ` Liu Shengzhou-B36685 2011-12-08 18:00 ` Scott Wood
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.