diff for duplicates of <4EE219B4.8030707@gmail.com> diff --git a/a/1.txt b/N1/1.txt index f89c738..aa2b75e 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -44,7 +44,7 @@ Acked-by: Rob Herring <rob.herring@calxeda.com> > + compatible = "nvidia,tegra30"; > + interrupt-parent = <&intc>; > + -> + intc: interrupt-controller@50041000 { +> + intc: interrupt-controller at 50041000 { > + compatible = "arm,cortex-a9-gic"; > + interrupt-controller; > + #interrupt-cells = <3>; @@ -52,7 +52,7 @@ Acked-by: Rob Herring <rob.herring@calxeda.com> > + < 0x50040100 0x0100 >; > + }; > + -> + i2c@7000c000 { +> + i2c at 7000c000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; @@ -60,7 +60,7 @@ Acked-by: Rob Herring <rob.herring@calxeda.com> > + interrupts = < 0 38 0x04 >; > + }; > + -> + i2c@7000c400 { +> + i2c at 7000c400 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; @@ -68,7 +68,7 @@ Acked-by: Rob Herring <rob.herring@calxeda.com> > + interrupts = < 0 84 0x04 >; > + }; > + -> + i2c@7000c500 { +> + i2c at 7000c500 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; @@ -76,7 +76,7 @@ Acked-by: Rob Herring <rob.herring@calxeda.com> > + interrupts = < 0 92 0x04 >; > + }; > + -> + i2c@7000c700 { +> + i2c at 7000c700 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; @@ -84,7 +84,7 @@ Acked-by: Rob Herring <rob.herring@calxeda.com> > + interrupts = < 0 120 0x04 >; > + }; > + -> + i2c@7000d000 { +> + i2c at 7000d000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; @@ -92,7 +92,7 @@ Acked-by: Rob Herring <rob.herring@calxeda.com> > + interrupts = < 0 53 0x04 >; > + }; > + -> + gpio: gpio@6000d000 { +> + gpio: gpio at 6000d000 { > + compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; > + reg = < 0x6000d000 0x1000 >; > + interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >; @@ -100,66 +100,66 @@ Acked-by: Rob Herring <rob.herring@calxeda.com> > + gpio-controller; > + }; > + -> + serial@70006000 { +> + serial at 70006000 { > + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; > + reg = <0x70006000 0x40>; > + reg-shift = <2>; > + interrupts = < 0 36 0x04 >; > + }; > + -> + serial@70006040 { +> + serial at 70006040 { > + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; > + reg = <0x70006040 0x40>; > + reg-shift = <2>; > + interrupts = < 0 37 0x04 >; > + }; > + -> + serial@70006200 { +> + serial at 70006200 { > + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; > + reg = <0x70006200 0x100>; > + reg-shift = <2>; > + interrupts = < 0 46 0x04 >; > + }; > + -> + serial@70006300 { +> + serial at 70006300 { > + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; > + reg = <0x70006300 0x100>; > + reg-shift = <2>; > + interrupts = < 0 90 0x04 >; > + }; > + -> + serial@70006400 { +> + serial at 70006400 { > + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; > + reg = <0x70006400 0x100>; > + reg-shift = <2>; > + interrupts = < 0 91 0x04 >; > + }; > + -> + sdhci@78000000 { +> + sdhci at 78000000 { > + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; > + reg = <0x78000000 0x200>; > + interrupts = < 0 14 0x04 >; > + }; > + -> + sdhci@78000200 { +> + sdhci at 78000200 { > + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; > + reg = <0x78000200 0x200>; > + interrupts = < 0 15 0x04 >; > + }; > + -> + sdhci@78000400 { +> + sdhci at 78000400 { > + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; > + reg = <0x78000400 0x200>; > + interrupts = < 0 19 0x04 >; > + }; > + -> + sdhci@78000600 { +> + sdhci at 78000600 { > + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; > + reg = <0x78000600 0x200>; > + interrupts = < 0 31 0x04 >; > + }; > + -> + pinmux: pinmux@70000000 { +> + pinmux: pinmux at 70000000 { > + compatible = "nvidia,tegra30-pinmux"; > + reg = < 0x70000868 0xd0 /* Pad control registers */ > + 0x70003000 0x3e0 >; /* Mux registers */ diff --git a/a/content_digest b/N1/content_digest index 331dfc8..0959efd 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,21 +1,9 @@ "ref\01323348254-29072-1-git-send-email-pdeschrijver@nvidia.com\0" "ref\01323348254-29072-2-git-send-email-pdeschrijver@nvidia.com\0" - "From\0Rob Herring <robherring2@gmail.com>\0" - "Subject\0Re: [PATCH v6 01/10] arm/tegra: initial device tree for tegra30\0" + "From\0robherring2@gmail.com (Rob Herring)\0" + "Subject\0[PATCH v6 01/10] arm/tegra: initial device tree for tegra30\0" "Date\0Fri, 09 Dec 2011 08:22:44 -0600\0" - "To\0Peter De Schrijver <pdeschrijver@nvidia.com>\0" - "Cc\0Grant Likely <grant.likely@secretlab.ca>" - Randy Dunlap <rdunlap@xenotime.net> - Russell King <linux@arm.linux.org.uk> - Colin Cross <ccross@android.com> - Olof Johansson <olof@lixom.net> - Stephen Warren <swarren@nvidia.com> - Gary King <gking@nvidia.com> - devicetree-discuss@lists.ozlabs.org - linux-doc@vger.kernel.org - linux-kernel@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-tegra@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 12/08/2011 06:43 AM, Peter De Schrijver wrote:\n" @@ -64,7 +52,7 @@ "> +\tcompatible = \"nvidia,tegra30\";\n" "> +\tinterrupt-parent = <&intc>;\n" "> +\n" - "> +\tintc: interrupt-controller@50041000 {\n" + "> +\tintc: interrupt-controller at 50041000 {\n" "> +\t\tcompatible = \"arm,cortex-a9-gic\";\n" "> +\t\tinterrupt-controller;\n" "> +\t\t#interrupt-cells = <3>;\n" @@ -72,7 +60,7 @@ "> +\t\t < 0x50040100 0x0100 >;\n" "> +\t};\n" "> +\n" - "> +\ti2c@7000c000 {\n" + "> +\ti2c at 7000c000 {\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\t\tcompatible = \"nvidia,tegra30-i2c\", \"nvidia,tegra20-i2c\";\n" @@ -80,7 +68,7 @@ "> +\t\tinterrupts = < 0 38 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\ti2c@7000c400 {\n" + "> +\ti2c at 7000c400 {\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\t\tcompatible = \"nvidia,tegra30-i2c\", \"nvidia,tegra20-i2c\";\n" @@ -88,7 +76,7 @@ "> +\t\tinterrupts = < 0 84 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\ti2c@7000c500 {\n" + "> +\ti2c at 7000c500 {\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\t\tcompatible = \"nvidia,tegra30-i2c\", \"nvidia,tegra20-i2c\";\n" @@ -96,7 +84,7 @@ "> +\t\tinterrupts = < 0 92 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\ti2c@7000c700 {\n" + "> +\ti2c at 7000c700 {\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\t\tcompatible = \"nvidia,tegra30-i2c\", \"nvidia,tegra20-i2c\";\n" @@ -104,7 +92,7 @@ "> +\t\tinterrupts = < 0 120 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\ti2c@7000d000 {\n" + "> +\ti2c at 7000d000 {\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\t\tcompatible = \"nvidia,tegra30-i2c\", \"nvidia,tegra20-i2c\";\n" @@ -112,7 +100,7 @@ "> +\t\tinterrupts = < 0 53 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\tgpio: gpio@6000d000 {\n" + "> +\tgpio: gpio at 6000d000 {\n" "> +\t\tcompatible = \"nvidia,tegra30-gpio\", \"nvidia,tegra20-gpio\";\n" "> +\t\treg = < 0x6000d000 0x1000 >;\n" "> +\t\tinterrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >;\n" @@ -120,70 +108,70 @@ "> +\t\tgpio-controller;\n" "> +\t};\n" "> +\n" - "> +\tserial@70006000 {\n" + "> +\tserial at 70006000 {\n" "> +\t\tcompatible = \"nvidia,tegra30-uart\", \"nvidia,tegra20-uart\";\n" "> +\t\treg = <0x70006000 0x40>;\n" "> +\t\treg-shift = <2>;\n" "> +\t\tinterrupts = < 0 36 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\tserial@70006040 {\n" + "> +\tserial at 70006040 {\n" "> +\t\tcompatible = \"nvidia,tegra30-uart\", \"nvidia,tegra20-uart\";\n" "> +\t\treg = <0x70006040 0x40>;\n" "> +\t\treg-shift = <2>;\n" "> +\t\tinterrupts = < 0 37 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\tserial@70006200 {\n" + "> +\tserial at 70006200 {\n" "> +\t\tcompatible = \"nvidia,tegra30-uart\", \"nvidia,tegra20-uart\";\n" "> +\t\treg = <0x70006200 0x100>;\n" "> +\t\treg-shift = <2>;\n" "> +\t\tinterrupts = < 0 46 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\tserial@70006300 {\n" + "> +\tserial at 70006300 {\n" "> +\t\tcompatible = \"nvidia,tegra30-uart\", \"nvidia,tegra20-uart\";\n" "> +\t\treg = <0x70006300 0x100>;\n" "> +\t\treg-shift = <2>;\n" "> +\t\tinterrupts = < 0 90 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\tserial@70006400 {\n" + "> +\tserial at 70006400 {\n" "> +\t\tcompatible = \"nvidia,tegra30-uart\", \"nvidia,tegra20-uart\";\n" "> +\t\treg = <0x70006400 0x100>;\n" "> +\t\treg-shift = <2>;\n" "> +\t\tinterrupts = < 0 91 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\tsdhci@78000000 {\n" + "> +\tsdhci at 78000000 {\n" "> +\t\tcompatible = \"nvidia,tegra30-sdhci\", \"nvidia,tegra20-sdhci\";\n" "> +\t\treg = <0x78000000 0x200>;\n" "> +\t\tinterrupts = < 0 14 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\tsdhci@78000200 {\n" + "> +\tsdhci at 78000200 {\n" "> +\t\tcompatible = \"nvidia,tegra30-sdhci\", \"nvidia,tegra20-sdhci\";\n" "> +\t\treg = <0x78000200 0x200>;\n" "> +\t\tinterrupts = < 0 15 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\tsdhci@78000400 {\n" + "> +\tsdhci at 78000400 {\n" "> +\t\tcompatible = \"nvidia,tegra30-sdhci\", \"nvidia,tegra20-sdhci\";\n" "> +\t\treg = <0x78000400 0x200>;\n" "> +\t\tinterrupts = < 0 19 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\tsdhci@78000600 {\n" + "> +\tsdhci at 78000600 {\n" "> +\t\tcompatible = \"nvidia,tegra30-sdhci\", \"nvidia,tegra20-sdhci\";\n" "> +\t\treg = <0x78000600 0x200>;\n" "> +\t\tinterrupts = < 0 31 0x04 >;\n" "> +\t};\n" "> +\n" - "> +\tpinmux: pinmux@70000000 {\n" + "> +\tpinmux: pinmux at 70000000 {\n" "> +\t\tcompatible = \"nvidia,tegra30-pinmux\";\n" "> +\t\treg = < 0x70000868 0xd0 /* Pad control registers */\n" "> +\t\t\t0x70003000 0x3e0 >; /* Mux registers */\n" "> +\t};\n" > +}; -ddb5e4b471aa332b0ed56c668d599fec45094ebf21467a6087961c8f12a1f410 +05683b831da0ab5b2851f9dd465c7e585a51f9b37e2ff8ba60d40e783b6a9fc0
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