Re: [Qemu-devel] [PATCH] target-arm: Fixed ARMv7-M SHPR access

[Sebastian Huber <sebastian.huber@embedded-brains.de>]

On 17/12/11 01:50, Peter Maydell wrote:
> On 16 December 2011 18:50, Sebastian Huber
> <sebastian.huber@embedded-brains.de>  wrote:
>> According to "ARMv7-M Architecture Reference Manual" issue D section
>> "B3.2.10 System Handler Prioriy Register 1, SHPR1", "B3.2.11 System
>> Handler Prioriy Register 2, SHPR2", and "B3.2.12 System Handler Prioriy
>> Register 3, SHPR3".
> This would fix the specific issue of not being able to do byte or halfword
> accesses to the SHPR registers, but it doesn't do anything about other
> byte-accessible registers like the CFSR.
>
> The right fix for this is for armv7m_nvic to expose a memory region for
> the system control space which implements byte and halfword accesses,
> and not to try to indirect everything through a single GIC region.

I am primary a Qemu user and fixed the bugs only as far as it was 
necessary to run my test suites.  I used the surrounding code as a 
reference.  Maybe I find some time in the next months to clean this up.

-- 
Sebastian Huber, embedded brains GmbH

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