From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:42916) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rd6tc-0003LH-E1 for qemu-devel@nongnu.org; Tue, 20 Dec 2011 16:06:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rd6tb-0004qU-A0 for qemu-devel@nongnu.org; Tue, 20 Dec 2011 16:06:48 -0500 Received: from smtp191.dfw.emailsrvr.com ([67.192.241.191]:54061) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rd6tb-0004qM-5S for qemu-devel@nongnu.org; Tue, 20 Dec 2011 16:06:47 -0500 Message-ID: <4EF0F8E8.9050702@calxeda.com> Date: Tue, 20 Dec 2011 15:06:48 -0600 From: Mark Langsdorf MIME-Version: 1.0 References: <4EF0DDEB.40302@calxeda.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 4/9] arm: add dummy gic security registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: "qemu-devel@nongnu.org" , "paul@codesourcery.com" On 12/20/2011 01:58 PM, Peter Maydell wrote: > On 20 December 2011 19:11, Mark Langsdorf wrote: >> From: Rob Herring >> >> Signed-off-by: Rob Herring >> Signed-off-by: Mark Langsdorf >> --- >> hw/arm_gic.c | 10 ++++++++-- >> 1 files changed, 8 insertions(+), 2 deletions(-) >> >> diff --git a/hw/arm_gic.c b/hw/arm_gic.c >> index 9b52119..5974c2f 100644 >> --- a/hw/arm_gic.c >> +++ b/hw/arm_gic.c >> @@ -274,7 +274,7 @@ static uint32_t gic_dist_readb(void *opaque, >> target_phys_addr_t offset) >> >> cpu = gic_get_current_cpu(); >> cm = 1<< cpu; >> - if (offset< 0x100) { >> + if (offset< 0x80) { >> #ifndef NVIC >> if (offset == 0) >> return s->enabled; >> @@ -284,6 +284,9 @@ static uint32_t gic_dist_readb(void *opaque, >> target_phys_addr_t offset) >> return 0; >> #endif >> goto bad_reg; >> + } else if (offset< 0x100) { >> + /* Interrupt Security */ >> + return 0; > > This won't actually break anything, but really the handling of 0x80..0xff > would be inside the first if() clause, because of the way we piggyback > the v7M NVIC off these functions. (We should clean that up, really). > Anyway, the v7M NVIC doesn't own 0x0..0xff, which is what the first > if () clause is marking off. Ditto in the write function. > > It would also be nice to have the comment explicitly say that these > registers are defined to RAZ/WI in GIC implementations that don't > implement the security extensions. > I'm not sure what changes you want made here. I can resubmit with the comment. But I don't know how qemu piggybacks the v7M NVIC so I don't understand what you want done. --Mark Langsdorf Calxeda, Inc.