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From: Alexey Korolev <alexey.korolev@endace.com>
To: "Michael S. Tsirkin" <mst@redhat.com>
Cc: sfd@endace.com, yamahata@valinux.co.jp, seabios@seabios.org,
	qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 3/3] Changes related to secondary buses and 64bit regions
Date: Fri, 30 Dec 2011 17:56:06 +1300	[thread overview]
Message-ID: <4EFD4466.4020405@endace.com> (raw)
In-Reply-To: <20111229161844.GD2300@redhat.com>

On 30/12/11 05:18, Michael S. Tsirkin wrote:
> On Thu, Dec 29, 2011 at 06:40:26PM +1300, Alexey Korolev wrote:
>> On 29/12/11 00:43, Michael S. Tsirkin wrote:
>>> On Wed, Dec 28, 2011 at 06:35:55PM +1300, Alexey Korolev wrote:
>>>> All devices behind a bridge need to have all their regions consecutive and
>>>> not overlapping with all the normal memory ranges.
>>>> Since prefetchable memory is described by one record, we must avoid the situations
>>>> when 32bit and 64bit prefetchable regions are present within one secondary bus.
>>> How do we avoid this? Assume we have two devices:
>>> a 32 bit and a 64 bit one, behind a bridge.
>>> There are two main things we can do:
>>> 1. Make the 64 bit device only use the low 32 bit
>>   It was my first implementation. Unfortunately older versions of
>> Linux (Like 2.6.18) hang during startup with this.
>> As far as I remember it was qemu-0.15 so may be 1.0 have no such an
>> issue. I will check this.
>>> 2. Put the 32 bit one in the non-prefetcheable range
>> I'd rather not do this. Bios should not change memory region types.
>> It will confuse guest OS drivers.
> It shouldn't, it's a legal behavious.
> Prefetcheable BAR allows certain optimizations but does not
> require them.
Well it is really difficult to say what is a "legal behavior".
Yes it is legal behavior for PCI operations. But it could be a problem 
in software .
I won't be surprised if a driver fail to start if we substitute the 
regions. It will be very hard
to check all possible cases.

  reply	other threads:[~2011-12-30  4:56 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-12-28  4:41 [Qemu-devel] [Seabios] [PATCH 0/3] 64bit PCI BARs allocations Alexey Korolev
2011-12-28  5:00 ` [Qemu-devel] [PATCH 1/3] Add new range above 4GB in _CRS table Alexey Korolev
2011-12-28  5:26 ` [Qemu-devel] [PATCH 2/3] Add a new PCI region type to supports 64 bit ranges Alexey Korolev
2011-12-28 11:30   ` Michael S. Tsirkin
2011-12-29  3:57     ` Alexey Korolev
2011-12-29  2:56   ` Kevin O'Connor
2011-12-29  5:00     ` Alexey Korolev
2011-12-30  5:57       ` Kevin O'Connor
2011-12-29  5:32     ` Alexey Korolev
2011-12-29 16:16       ` Michael S. Tsirkin
2012-01-03 15:14     ` Gerd Hoffmann
2012-01-04  3:10       ` Kevin O'Connor
2011-12-28  5:35 ` [Qemu-devel] [PATCH 3/3] Changes related to secondary buses and 64bit regions Alexey Korolev
2011-12-28  6:30   ` [Qemu-devel] [SeaBIOS] " Alexey Korolev
2011-12-28 11:43   ` [Qemu-devel] " Michael S. Tsirkin
2011-12-29  5:40     ` Alexey Korolev
2011-12-29 16:18       ` Michael S. Tsirkin
2011-12-30  4:56         ` Alexey Korolev [this message]
2011-12-29  5:41     ` Alexey Korolev
2011-12-29 16:19       ` Michael S. Tsirkin
2011-12-29 16:21       ` Michael S. Tsirkin
2011-12-30  5:10         ` Alexey Korolev
2011-12-30  6:02           ` Kevin O'Connor
2011-12-30  5:10         ` Alexey Korolev
2011-12-30  6:22       ` Kevin O'Connor
2011-12-30  7:05         ` Alexey Korolev
2011-12-30  5:03     ` Kevin O'Connor
2011-12-28 11:43 ` [Qemu-devel] [Seabios] [PATCH 0/3] 64bit PCI BARs allocations Michael S. Tsirkin
2011-12-29  9:20   ` Alexey Korolev
2011-12-29 16:21     ` Michael S. Tsirkin
2011-12-29 22:17       ` Alexey Korolev

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