From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:54013) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rkpa3-00008W-78 for qemu-devel@nongnu.org; Tue, 10 Jan 2012 23:14:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rkpa1-0004Du-N9 for qemu-devel@nongnu.org; Tue, 10 Jan 2012 23:14:31 -0500 Received: from cantor2.suse.de ([195.135.220.15]:35039 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rkpa1-0004DQ-Ac for qemu-devel@nongnu.org; Tue, 10 Jan 2012 23:14:29 -0500 Message-ID: <4F0D0C3E.8080706@suse.de> Date: Wed, 11 Jan 2012 05:12:46 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1326213943-878-1-git-send-email-mark.langsdorf@calxeda.com> <1326227599-5257-1-git-send-email-mark.langsdorf@calxeda.com> <1326227599-5257-3-git-send-email-mark.langsdorf@calxeda.com> In-Reply-To: <1326227599-5257-3-git-send-email-mark.langsdorf@calxeda.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v7 2/6] arm: make the number of GIC interrupts configurable List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Langsdorf Cc: i.mitsyanko@gmail.com, peter.maydell@linaro.org, qemu-devel@nongnu.org, edgar.iglesias@gmail.com Am 10.01.2012 21:33, schrieb Mark Langsdorf: > Increase the maximum number of GIC interrupts for a9mp and a11mp to 102= 0, > and create a configurable property for each defaulting to 96 and 64 > (respectively) so that device modelers can set the value appropriately > for their SoC. Other ARM processors also set their maximum number of > used IRQs appropriately. >=20 > Set the maximum theoretical number of GIC interrupts to 1020 and > update the save/restore code to only use the appropriate number for > each SoC. >=20 > Signed-off-by: Mark Langsdorf > --- > Changes from v6 > Removed trailing whitespace > armv7m_nvic uses num_irq properly > Some comments changed > Changes from v5 > Clarify the commit message > Rename GIC_NIRQ to GIC_MAXIRQ and change usage slightly > Makes num-irq to uint32_t in all cases > Clarify the error message > Clarify documentation on the num-irq qdev property use in all f= iles > Changes from v4 > None > Changes from v3 > Increase maximum number of GIC interrupts to 1020 > Remove SoC/implementation specific GIC_NIRQ #defs > Added properties code to arm11mp > Changed error handling for too many interrupts > Redid save/load handling > Changes from v2 > Skipped > Changes from v1 > Increase the number of a9mp interrupts to 192 > Add a property defaulting to 96 > Add a num_irq member in the gic state structure > Use the num_irq value as appropriate > Add num_irq argument to gic_init() > Add num_irq to various CPU calls to gic_init >=20 > hw/a9mpcore.c | 13 +++++++-- > hw/arm11mpcore.c | 17 ++++++++---- > hw/arm_gic.c | 68 +++++++++++++++++++++++++++++----------------= ------- > hw/armv7m_nvic.c | 30 ++++++++++++++++++----- > hw/realview_gic.c | 7 ++++- > 5 files changed, 87 insertions(+), 48 deletions(-) > diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c > index bf8c3c5..befdc16 100644 > --- a/hw/armv7m_nvic.c > +++ b/hw/armv7m_nvic.c > @@ -384,16 +382,34 @@ static int armv7m_nvic_init(SysBusDevice *dev) > { > nvic_state *s=3D FROM_SYSBUSGIC(nvic_state, dev); > =20 > - gic_init(&s->gic); > + /* note that for the M profile gic_init() takes the number of exter= nal > + * interrupt lines only. > + */ > + gic_init(&s->gic, s->num_irq); > memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->g= ic.iomem); > s->systick.timer =3D qemu_new_timer_ns(vm_clock, systick_timer_tic= k, s); > vmstate_register(&dev->qdev, -1, &vmstate_nvic, s); This should probably be removed now that you register it through sysbus_register_withprop() below. > return 0; > } > =20 > +static SysBusDeviceInfo armv7m_nvic_priv_info =3D { > + .init =3D armv7m_nvic_init, > + .qdev.name =3D "armv7m_nvic", > + .qdev.size =3D sizeof(nvic_state), > + .qdev.vmsd =3D &vmstate_nvic, Minor nit: Assignment is inconsistent - add a space here? > + .qdev.props =3D (Property[]) { > + /* The ARM v7m may have anything from 0 to 496 external interr= upt > + * IRQ lines. We default to 64 external and 32 internal > + * Other boards may differ and should set this property approp= riately. > + */ > + DEFINE_PROP_UINT32("num-irq", nvic_state, num_irq, 64), > + DEFINE_PROP_END_OF_LIST(), > + } > +}; > + > static void armv7m_nvic_register_devices(void) > { > - sysbus_register_dev("armv7m_nvic", sizeof(nvic_state), armv7m_nvic= _init); > + sysbus_register_withprop(&armv7m_nvic_priv_info); > } > =20 > device_init(armv7m_nvic_register_devices) I'm still wondering whether the num-irq property calls for a version bump somewhere. My thinking is no, since the SysBus device will not be user-created from the command line and therefore effectively has the same values as hardcoded before; but in that case we should assert this by setting .qdev.no_user =3D 1. Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg