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diff for duplicates of <4F16EB24.4000701@gmail.com>

diff --git a/a/1.txt b/N1/1.txt
index 89e81af..45de722 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -38,14 +38,14 @@ Rob
 > The GIC device tree bindings documentation is updated by the patch
 > accordingly.
 > 
-> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-> Cc: Catalin Marinas <catalin.marinas@arm.com>
-> Cc: Will Deacon <will.deacon@arm.com>
-> Cc: Russell King <linux@arm.linux.org.uk>
-> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-> Cc: Grant Likely <grant.likely@secretlab.ca>
-> Cc: Rob Herring <rob.herring@calxeda.com>
-> Cc: Vincent Guittot <vincent.guittot@linaro.org>
+> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
+> Cc: Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>
+> Cc: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
+> Cc: Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
+> Cc: Benjamin Herrenschmidt <benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>
+> Cc: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>
+> Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
+> Cc: Vincent Guittot <vincent.guittot-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
 > ---
 >  Documentation/devicetree/bindings/arm/gic.txt |   69 ++++++++++++++++++
 >  arch/arm/common/gic.c                         |   94 +++++++++++++++++++++++-
@@ -75,28 +75,28 @@ Rob
 > +		#size-cells = <0>;
 > +		#address-cells = <1>;
 > +
-> +		CPU0: cpu at 0x0 {
+> +		CPU0: cpu@0x0 {
 > +			device_type = "cpu";
 > +			reg = <0x0>;
 > +		};
 > +
-> +		CPU1: cpu at 0x1 {
+> +		CPU1: cpu@0x1 {
 > +			device_type = "cpu";
 > +			reg = <0x1>;
 > +		};
 > +
-> +		CPU2: cpu at 0x100 {
+> +		CPU2: cpu@0x100 {
 > +			device_type = "cpu";
 > +			reg = <0x100>;
 > +		};
 > +
-> +		CPU3: cpu at 0x101 {
+> +		CPU3: cpu@0x101 {
 > +			device_type = "cpu";
 > +			reg = <0x101>;
 > +		};
 > +	};
 > +
-> +	intc: interrupt-controller at fff11000 {
+> +	intc: interrupt-controller@fff11000 {
 > +		compatible = "arm,cortex-a9-gic";
 > +		#interrupt-cells = <3>;
 > +		#address-cells = <1>;
@@ -104,25 +104,25 @@ Rob
 > +		reg = <0xfff11000 0x1000>,
 > +		      <0xfff10100 0x100>;
 > +
-> +			gic-cpuif at 0x0 {
+> +			gic-cpuif@0x0 {
 > +				compatible = "arm,gic-cpuif";
 > +				cpuif-id = <0x0>;
 > +				cpu = <&CPU0>;
 > +			};
 > +
-> +			gic-cpuif at 0x1 {
+> +			gic-cpuif@0x1 {
 > +				compatible = "arm,gic-cpuif";
 > +				cpuif-id = <0x1>;
 > +				cpu = <&CPU1>;
 > +			};
 > +
-> +			gic-cpuif at 0x2 {
+> +			gic-cpuif@0x2 {
 > +				compatible = "arm,gic-cpuif";
 > +				cpuif-id = <0x2>;
 > +				cpu = <&CPU2>;
 > +			};
 > +
-> +			gic-cpuif at 0x3 {
+> +			gic-cpuif@0x3 {
 > +				compatible = "arm,gic-cpuif";
 > +				cpuif-id = <0x3>;
 > +				cpu = <&CPU3>;
diff --git a/a/content_digest b/N1/content_digest
index 74d9b09..a19b252 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,9 +1,15 @@
  "ref\01326897408-11204-1-git-send-email-lorenzo.pieralisi@arm.com\0"
  "ref\01326897408-11204-5-git-send-email-lorenzo.pieralisi@arm.com\0"
- "From\0robherring2@gmail.com (Rob Herring)\0"
- "Subject\0[RFC PATCH 4/5] ARM: gic: add cpuif topology description\0"
+ "ref\01326897408-11204-5-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org\0"
+ "From\0Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0"
+ "Subject\0Re: [RFC PATCH 4/5] ARM: gic: add cpuif topology description\0"
  "Date\0Wed, 18 Jan 2012 09:54:12 -0600\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>\0"
+ "Cc\0Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>"
+  Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>
+  devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
+  Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
+ " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0"
  "\00:1\0"
  "b\0"
  "On 01/18/2012 08:36 AM, Lorenzo Pieralisi wrote:\n"
@@ -46,14 +52,14 @@
  "> The GIC device tree bindings documentation is updated by the patch\n"
  "> accordingly.\n"
  "> \n"
- "> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n"
- "> Cc: Catalin Marinas <catalin.marinas@arm.com>\n"
- "> Cc: Will Deacon <will.deacon@arm.com>\n"
- "> Cc: Russell King <linux@arm.linux.org.uk>\n"
- "> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>\n"
- "> Cc: Grant Likely <grant.likely@secretlab.ca>\n"
- "> Cc: Rob Herring <rob.herring@calxeda.com>\n"
- "> Cc: Vincent Guittot <vincent.guittot@linaro.org>\n"
+ "> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>\n"
+ "> Cc: Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>\n"
+ "> Cc: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\n"
+ "> Cc: Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>\n"
+ "> Cc: Benjamin Herrenschmidt <benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>\n"
+ "> Cc: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>\n"
+ "> Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>\n"
+ "> Cc: Vincent Guittot <vincent.guittot-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\n"
  "> ---\n"
  ">  Documentation/devicetree/bindings/arm/gic.txt |   69 ++++++++++++++++++\n"
  ">  arch/arm/common/gic.c                         |   94 +++++++++++++++++++++++-\n"
@@ -83,28 +89,28 @@
  "> +\t\t#size-cells = <0>;\n"
  "> +\t\t#address-cells = <1>;\n"
  "> +\n"
- "> +\t\tCPU0: cpu at 0x0 {\n"
+ "> +\t\tCPU0: cpu@0x0 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\treg = <0x0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU1: cpu at 0x1 {\n"
+ "> +\t\tCPU1: cpu@0x1 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\treg = <0x1>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU2: cpu at 0x100 {\n"
+ "> +\t\tCPU2: cpu@0x100 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\treg = <0x100>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tCPU3: cpu at 0x101 {\n"
+ "> +\t\tCPU3: cpu@0x101 {\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\treg = <0x101>;\n"
  "> +\t\t};\n"
  "> +\t};\n"
  "> +\n"
- "> +\tintc: interrupt-controller at fff11000 {\n"
+ "> +\tintc: interrupt-controller@fff11000 {\n"
  "> +\t\tcompatible = \"arm,cortex-a9-gic\";\n"
  "> +\t\t#interrupt-cells = <3>;\n"
  "> +\t\t#address-cells = <1>;\n"
@@ -112,25 +118,25 @@
  "> +\t\treg = <0xfff11000 0x1000>,\n"
  "> +\t\t      <0xfff10100 0x100>;\n"
  "> +\n"
- "> +\t\t\tgic-cpuif at 0x0 {\n"
+ "> +\t\t\tgic-cpuif@0x0 {\n"
  "> +\t\t\t\tcompatible = \"arm,gic-cpuif\";\n"
  "> +\t\t\t\tcpuif-id = <0x0>;\n"
  "> +\t\t\t\tcpu = <&CPU0>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tgic-cpuif at 0x1 {\n"
+ "> +\t\t\tgic-cpuif@0x1 {\n"
  "> +\t\t\t\tcompatible = \"arm,gic-cpuif\";\n"
  "> +\t\t\t\tcpuif-id = <0x1>;\n"
  "> +\t\t\t\tcpu = <&CPU1>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tgic-cpuif at 0x2 {\n"
+ "> +\t\t\tgic-cpuif@0x2 {\n"
  "> +\t\t\t\tcompatible = \"arm,gic-cpuif\";\n"
  "> +\t\t\t\tcpuif-id = <0x2>;\n"
  "> +\t\t\t\tcpu = <&CPU2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tgic-cpuif at 0x3 {\n"
+ "> +\t\t\tgic-cpuif@0x3 {\n"
  "> +\t\t\t\tcompatible = \"arm,gic-cpuif\";\n"
  "> +\t\t\t\tcpuif-id = <0x3>;\n"
  "> +\t\t\t\tcpu = <&CPU3>;\n"
@@ -277,4 +283,4 @@
  ">  \t/*\n"
  ">  \t * Ensure that stores to Normal memory are visible to the"
 
-10f2c1469b3f8c63148910c775d22e19ae3841cdfe99b39ac3340f06689472ce
+3af2f850bfdc1b736cd0f4088230d7a15a640b090681dedbb8dc8bcecddacd99

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