Re: [Qemu-devel] [PATCH 6/6] PPC: booke206: Implement tlbilx

[Scott Wood <scottwood@freescale.com>]

On 01/19/2012 09:17 PM, Alexander Graf wrote:
> +    case 3:
> +        /* flush by pid and ea */
> +        for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
> +            int ways = booke206_tlb_ways(env, i);
> +
> +            for (j = 0; j < ways; j++) {
> +                tlb = booke206_get_tlbm(env, i, address, j);
> +                if ((ppcmas_tlb_check(env, tlb, NULL, address, pid) != 0) ||
> +                    (tlb->mas1 & MAS1_IPROT) ||
> +                    ((tlb->mas1 & MAS1_TS) != ts) ||
> +                    ((tlb->mas1 & MAS1_IND) != ind) ||
> +                    ((tlb->mas1 & MAS1_TSIZE_MASK) != size) ||
> +                    ((tlb->mas8 & MAS8_TGS) != sgs)) {
> +                        continue;
> +                }
> +                tlb->mas1 &= ~MAS1_VALID;
> +            }

ISIZE is only supported on MAV=2.0, and then only if TLB write
conditional or Hardware Entry Select is supported.

Also, I don't know to what extent you want to emulate particular cores
versus a generic implementation of the architecture, but e500mc does not
filter on MAS6[SAS].  This is permitted as noted in 6.7.1's Programming
Note allowing generous TLB invalidations, and is documented this way in
the e500mc manual so software could be relying on it.

-Scott