From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kenneth Graunke Subject: Re: [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting. Date: Sat, 21 Jan 2012 02:57:49 -0800 Message-ID: <4F1A9A2D.1030705@whitecape.org> References: <1326999006-15100-1-git-send-email-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from homiemail-a5.g.dreamhost.com (caiajhbdccah.dreamhost.com [208.97.132.207]) by gabe.freedesktop.org (Postfix) with ESMTP id C4F9F9E73F for ; Sat, 21 Jan 2012 02:57:50 -0800 (PST) In-Reply-To: <1326999006-15100-1-git-send-email-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eric Anholt Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On 01/19/2012 10:50 AM, Eric Anholt wrote: > We have always been using the wrong bit -- it's bit 12. However, the > bit also doesn't do anything -- hardware has always accepted the > MI_FLUSH command even when it was specced not to. > > Given that there is only one MI_FLUSH emitted in all of the driver > stack on gen6+ (in i965_video.c of the 2d driver, and it should be > using other code to do its flush instead), just remove the MI_FLUSH > enable instead of trying to fix it. > > Signed-off-by: Eric Anholt > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 -- > 1 files changed, 0 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 2df35e3..d21346b 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -389,8 +389,6 @@ static int init_render_ring(struct intel_ring_buffer *ring) > > if (INTEL_INFO(dev)->gen> 3) { > int mode = VS_TIMER_DISPATCH<< 16 | VS_TIMER_DISPATCH; > - if (IS_GEN6(dev) || IS_GEN7(dev)) > - mode |= MI_FLUSH_ENABLE<< 16 | MI_FLUSH_ENABLE; > I915_WRITE(MI_MODE, mode); > if (IS_GEN7(dev)) > I915_WRITE(GFX_MODE_GEN7, Everything using MI_FLUSH on SNB+ ought to be converted to PIPE_CONTROL. It sounds like everything except i965_video is there already. There's still the issue of old userspace, but...given that we were setting the wrong bit and _not_ setting the actual MI_FLUSH enable bit...it seems like this patch shouldn't break things. I'm all in favor of removing this code, as it's definitely a lie. For both patches: Reviewed-by: Kenneth Graunke