From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jan Kiszka Subject: Re: [PATCH] reset edge sense circuit of i8259 on init Date: Tue, 24 Jan 2012 16:06:02 +0100 Message-ID: <4F1EC8DA.7090008@siemens.com> References: <20120124130605.GA9571@redhat.com> <4F1EB5AF.1090006@siemens.com> <20120124134628.GB9571@redhat.com> <4F1EB6E4.5010801@siemens.com> <20120124135415.GC9571@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: "kvm@vger.kernel.org" , "avi@redhat.com" , "mtosatti@redhat.com" To: Gleb Natapov Return-path: Received: from thoth.sbs.de ([192.35.17.2]:34923 "EHLO thoth.sbs.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751867Ab2AXPGI (ORCPT ); Tue, 24 Jan 2012 10:06:08 -0500 In-Reply-To: <20120124135415.GC9571@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: On 2012-01-24 14:54, Gleb Natapov wrote: > On Tue, Jan 24, 2012 at 02:49:24PM +0100, Jan Kiszka wrote: >> On 2012-01-24 14:46, Gleb Natapov wrote: >>> On Tue, Jan 24, 2012 at 02:44:15PM +0100, Jan Kiszka wrote: >>>> On 2012-01-24 14:06, Gleb Natapov wrote: >>>>> The spec says that during initialization "The edge sense circuit is >>>>> reset which means that following initialization an interrupt request >>>>> (IR) input must make a low-to-high transition to generate an interrupt", >>>>> but currently if edge triggered interrupt is in IRR it is delivered >>>>> after i8259 initialization. >>>>> >>>>> Signed-off-by: Gleb Natapov >>>>> diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c >>>>> index b6a7353..81cf4fa 100644 >>>>> --- a/arch/x86/kvm/i8259.c >>>>> +++ b/arch/x86/kvm/i8259.c >>>>> @@ -307,6 +307,7 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val) >>>>> if (val & 0x10) { >>>>> s->init4 = val & 1; >>>>> s->last_irr = 0; >>>>> + s->irr &= s->elcr; >>>> >>>> Does & elcr make a relevant difference? QEMU simply sets irr to 0. If >>>> that's an issue, we need to fix both. >>>> >>> I saw what QEMU does. It's hard to tell looking at the spec what's more >>> correct. I think by zeroing irr we may lose level triggered interrupts >>> that happened just before init. >> >> Right. If those are supposed to get through despite init, then it is a >> QEMU bug. Will read the spec again as well. >> > On real HW they should go through if the IR line is still high. Looks like. IMR is cleared, so a level-triggered IRQ is free to pass and set IRR again - even if the chip clears it internally. Will write a patch. Jan -- Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux