From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:33002) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rq3Ry-0007hP-GH for qemu-devel@nongnu.org; Wed, 25 Jan 2012 09:03:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rq3Ro-00061Y-Uo for qemu-devel@nongnu.org; Wed, 25 Jan 2012 09:03:46 -0500 Received: from cantor2.suse.de ([195.135.220.15]:36173 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rq3Ro-00061J-LE for qemu-devel@nongnu.org; Wed, 25 Jan 2012 09:03:36 -0500 Message-ID: <4F200B37.9090501@suse.de> Date: Wed, 25 Jan 2012 15:01:27 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1327498343-5830-1-git-send-email-peter.maydell@linaro.org> <1327498343-5830-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1327498343-5830-2-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 1/2] Add dummy implementation of generic timer cp15 registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org Am 25.01.2012 14:32, schrieb Peter Maydell: > Add a dummy implementation of the cp15 registers for the generic > timer (found in the Cortex-A15), just sufficient for Linux to > decide that it can't use it. This requires at least CNTP_CTL and > CNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14. >=20 > Signed-off-by: Peter Maydell Reviewed-by: Andreas F=E4rber Took me a bit to figure out RAZ/WI. ;) Andreas > --- > target-arm/cpu.h | 1 + > target-arm/helper.c | 12 ++++++++++-- > 2 files changed, 11 insertions(+), 2 deletions(-) >=20 > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 42c53a7..7442c99 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -382,6 +382,7 @@ enum arm_features { > ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ > ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ > ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ > + ARM_FEATURE_GENERIC_TIMER, > }; > =20 > static inline int arm_feature(CPUARMState *env, int feature) > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 22e40fc..5e7205a 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1764,7 +1764,11 @@ void HELPER(set_cp15)(CPUState *env, uint32_t in= sn, uint32_t val) > goto bad_reg; > } > break; > - case 14: /* Reserved. */ > + case 14: /* Generic timer */ > + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { > + /* Dummy implementation: RAZ/WI for all */ > + break; > + } > goto bad_reg; > case 15: /* Implementation specific. */ > if (arm_feature(env, ARM_FEATURE_XSCALE)) { > @@ -2134,7 +2138,11 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_= t insn) > default: > goto bad_reg; > } > - case 14: /* Reserved. */ > + case 14: /* Generic timer */ > + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { > + /* Dummy implementation: RAZ/WI for all */ > + return 0; > + } > goto bad_reg; > case 15: /* Implementation specific. */ > if (arm_feature(env, ARM_FEATURE_XSCALE)) { --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg