From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aneesh V Subject: Re: OMAP3 L2/outer cache enabled in kernel (after being disabled by uBoot)? Date: Tue, 31 Jan 2012 10:51:50 +0530 Message-ID: <4F277A6E.9070107@ti.com> References: <20120116131329.GA928@n2100.arm.linux.org.uk> <20120117121138.GC11475@arm.com> <4F15692D.4070100@ti.com> <20120117133918.GE11475@arm.com> <20120127173029.GA3281@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-path: Received: from na3sys009aog124.obsmtp.com ([74.125.149.151]:43236 "EHLO na3sys009aog124.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751754Ab2AaFV6 (ORCPT ); Tue, 31 Jan 2012 00:21:58 -0500 Received: by dadi2 with SMTP id i2so4187229dad.19 for ; Mon, 30 Jan 2012 21:21:57 -0800 (PST) In-Reply-To: <20120127173029.GA3281@arm.com> Sender: linux-omap-owner@vger.kernel.org List-Id: linux-omap@vger.kernel.org To: Catalin Marinas Cc: Joe Woodward , "Shilimkar, Santosh" , Russell King - ARM Linux , "linux-omap@vger.kernel.org" , linux-arm Hi Catalin, On Friday 27 January 2012 11:00 PM, Catalin Marinas wrote: > On Fri, Jan 20, 2012 at 08:57:11AM +0000, Joe Woodward wrote: >>> So I re-iterate that we need to have solution to this problem. >> >> ... I don't want to be a pain, but it seems to me that this dicussion >> didn't reach a full conclussion? > > Probably not, because it depends on many variables. See below my take on > this. > >> I think it was left with the open options being: >> 1) Leave the L2/outer cache enabled in the bootloader (not ideal and >> may cause problems with future devices) > > This depends on whether the L2 is inner or outer: > > L2 inner - leave it enabled in the boot loader > L2 outer - leave it disabled in the boot loader > >> 2) Turn the L2/outer cache on for OMAP3 later in the kernel boot when >> the device is known > > Same as above: > > L2 inner - don't do anything, it gets used when SCTLR.M is enabled > L2 outer - enabled at boot time via the platform code (later, after MMU > was enabled). > What is the reasoning behind this recommendation? Why the distinction between L2 being inner or outer. I don't see anything to this effect in the Cortex-A8 TRM? In fact the only recommendation I could find(section 8.3) is asking to set L2EN to 1 before setting C bit to 1 irrespective of inner/outer? br, Aneesh From mboxrd@z Thu Jan 1 00:00:00 1970 From: aneesh@ti.com (Aneesh V) Date: Tue, 31 Jan 2012 10:51:50 +0530 Subject: OMAP3 L2/outer cache enabled in kernel (after being disabled by uBoot)? In-Reply-To: <20120127173029.GA3281@arm.com> References: <20120116131329.GA928@n2100.arm.linux.org.uk> <20120117121138.GC11475@arm.com> <4F15692D.4070100@ti.com> <20120117133918.GE11475@arm.com> <20120127173029.GA3281@arm.com> Message-ID: <4F277A6E.9070107@ti.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Catalin, On Friday 27 January 2012 11:00 PM, Catalin Marinas wrote: > On Fri, Jan 20, 2012 at 08:57:11AM +0000, Joe Woodward wrote: >>> So I re-iterate that we need to have solution to this problem. >> >> ... I don't want to be a pain, but it seems to me that this dicussion >> didn't reach a full conclussion? > > Probably not, because it depends on many variables. See below my take on > this. > >> I think it was left with the open options being: >> 1) Leave the L2/outer cache enabled in the bootloader (not ideal and >> may cause problems with future devices) > > This depends on whether the L2 is inner or outer: > > L2 inner - leave it enabled in the boot loader > L2 outer - leave it disabled in the boot loader > >> 2) Turn the L2/outer cache on for OMAP3 later in the kernel boot when >> the device is known > > Same as above: > > L2 inner - don't do anything, it gets used when SCTLR.M is enabled > L2 outer - enabled at boot time via the platform code (later, after MMU > was enabled). > What is the reasoning behind this recommendation? Why the distinction between L2 being inner or outer. I don't see anything to this effect in the Cortex-A8 TRM? In fact the only recommendation I could find(section 8.3) is asking to set L2EN to 1 before setting C bit to 1 irrespective of inner/outer? br, Aneesh