From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:59168) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RyMWp-0001aN-Ly for qemu-devel@nongnu.org; Fri, 17 Feb 2012 07:03:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RyMWl-0004vp-9v for qemu-devel@nongnu.org; Fri, 17 Feb 2012 07:03:07 -0500 Received: from cantor2.suse.de ([195.135.220.15]:57936 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RyMWl-0004uM-0Y for qemu-devel@nongnu.org; Fri, 17 Feb 2012 07:03:03 -0500 Message-ID: <4F3E41F4.8090407@suse.de> Date: Fri, 17 Feb 2012 13:03:00 +0100 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1328237992-14953-1-git-send-email-afaerber@suse.de> <1328237992-14953-15-git-send-email-afaerber@suse.de> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH RFC v3 14/21] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: andrzej zaborowski Cc: Peter Maydell , qemu-devel@nongnu.org, Paul Brook Am 17.02.2012 10:59, schrieb andrzej zaborowski: > On 3 February 2012 03:59, Andreas F=C3=A4rber wrote: >> No other emulated CPU uses this at this time. >=20 > But why does this code better fit in hw/ than target-arm? The iwMMXt > registers are core registers after all. It seems you've misread something here. This is all in target-arm. :) > Also the defines let the board code request a cpu revision by name > instead of using a magic number, so I think they're useful. No, the boards request a CPU by type name, which is not magic either. The whole point of QOM'ification is to have the CPU provide the necessary fields and methods, not logic spread across the code in an if-this-cpu-then fashion. I plan to tackle cp15 (the last remainder of CPUID code dependencies) when I'm through with all other targets. If someone really needs the CPUID they can access it through ARMCPU (CPUARMState). The final plan for rnpn is to have two QOM properties and to request a "pxa270" CPU, then set the revision since there are no functional dependencies on the revision at all. (cc'ing Paul) I've actually compile-tested and grep'ed this. Please note also the following v4 that came out of an IRC discussion: http://repo.or.cz/w/qemu/afaerber.git/commitdiff/1262acf06308cf2bde46520d= 0238548cb73c79fe If you need the JTAG_ID somewhere please let us know soon. Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg